Method and apparatus for deskewing decentralized data streams

Patent metadata

Field	Value
Publication number	US-2019121758-A1
Application number	US-201715788899-A
Country	US
Kind code	A1
Filing date	Oct 20, 2017
Priority date	Oct 20, 2017
Publication date	Apr 25, 2019
Grant date	—

Abstract

In one embodiment, a method includes receiving an input signal at a local data lane comprising a dynamic entry shift register, the input signal comprising a marker also received at a remote data lane, identifying receipt of the marker in the local data lane, starting a timer and notifying the remote data lane that the marker was found, receiving a marker found status from the remote data lane and saving a value of the timer, calculating a compensated delay for the remote data lane based on the timer value and a number of pipeline stages for the remote data lane, and setting an entry point to the dynamic entry shift register based on the compensated delay to deskew data between the local data lane and the remote data lane.

First claim

1 . A method comprising:
storing a number of pipeline stages associated with a remote data lane at a local data lane; receiving an input signal at the local data lane comprising a dynamic entry shift register, the input signal comprising a marker also received at the remote data lane; identifying receipt of the marker at a deskew module in the local data lane and in response to identifying receipt of the marker, starting a timer at the local data lane and notifying the remote data lane and all other remote data lanes receiving the input signal that the marker was found via a pipeline structure; receiving at the deskew module, a marker found status from the remote data lane at a communication link; storing at the deskew module a value of the timer when the marker found status was received, wherein the value of the timer represents a marker found delay for the remote data lane; calculating at the deskew module, a compensated delay for the remote data lane based on the timer value and the number of pipeline stages associated with the remote data lane; and setting an entry point to the dynamic entry shift register based on a maximum compensated delay calculated for the remote data lane and any other remote data lanes to deskew data between the local data lane and the one or more remote data lanes, wherein the local data lane and the one or more remote data lanes are physically isolated or separated by distance.

2 . The method of claim 1 wherein the maximum compensated delay represents a data skew between the local data lane and the remote data lane of all of the remote data lanes receiving the marker last.

3 . The method of claim 1 wherein the remote data lane comprises the dynamic entry shift register and the deskew module, and is configured to calculate the compensated delay for all of its respective remote data lanes and set the entry point to the dynamic entry shift register.

4 . The method of claim 1 wherein the local data lane is located on a separate die of a semiconductor chip.

5 . The method of claim 1 wherein the local data lane and the remote data lane are located in different sections of a semiconductor chip die.

6 . The method of claim 5 wherein the semiconductor chip comprises a 2.5 dimensional chip and the communication link comprises a chip-to-chip interface.

7 . The method of claim 1 further comprising storing a pipeline delay for the remote data lane based on the number of pipeline stages associated with the remote data lane.

8 . The method of claim 7 further comprising comparing the timer value to the pipeline delay plus a maximum depth of the dynamic entry shift register and detecting an error if the timer value is greater than the sum of the pipeline delay and the maximum depth of the dynamic entry shift register.

9 . The method of claim 1 wherein calculating the compensated delay for the remote data lane comprises subtracting the number of pipeline stages from the timer value for the remote data lane.

10 . The method of claim 9 wherein the compensated delay is negative and further comprising normalizing the compensated delay to zero.

11 . An apparatus comprising:
a plurality of data lanes configured to receive input signals comprising a marker, each of the data lanes comprising a dynamic entry shift register, a timer, and memory for storing a number of pipeline stages for each of the other data lanes; a plurality of deskew modules, each of the deskew modules located at one of the data lanes and configured for identifying receipt of the marker at the data lane and in response to identifying receipt of the marker, starting the timer at the data lane and notifying all of the other data lanes that the marker was found via a pipeline structure, receiving a marker found status from each of the other data lanes and saving a value of the timer when the marker found status was received, calculating a compensated delay for each of the other data lanes based on the timer value and the number of pipeline stages for the data lane, and setting an entry point to the dynamic entry shift register based on a maximum compensated delay calculated for the other data lanes to deskew data between the data lanes; and memory for storing a number of pipeline stages associated with the data lanes and a value of the time when the marker found status was received, wherein the value of the time represents a marker found delay for the remote data lane; wherein at least two of the data lanes are physically isolated or separated by distance.

12 . The apparatus of claim 11 wherein the plurality of data lanes are located in different regions of a semiconductor chip die.

13 . The apparatus of claim 11 wherein at least two of the data lanes are located on different die of a semiconductor chip and notification that the marker was found is transmitted via a chip-to-chip interface.

14 . The apparatus of claim 11 wherein the notification that the marker was found is transmitted via a pipeline structure.

15 . The apparatus of claim 11 wherein the number of pipeline stages defines a pipeline delay between two of the data lanes.

16 . The apparatus of claim 15 wherein the deskew module is further operable to compare the timer value to the pipeline delay plus a maximum depth of the dynamic entry shift register and detect an error if the timer value is greater than the sum of the pipeline delay and the maximum depth of the dynamic entry shift register.

17 . The apparatus of claim 11 wherein calculating the compensated delay for one of the other data lanes comprises subtracting the number of pipeline stages from the timer value for the data lane.

18 . A method comprising:
receiving data at a die comprising a plurality of data lanes, each of said plurality of data lanes comprising a dynamic entry shift register and a deskew module; identifying receipt of a marker at each of the deskew modules, and in response to identifying receipt of the marker, starting a timer and notifying the other deskew modules that the marker was found; receiving at each of the deskew modules, a marker found status from the other deskew modules and saving a value of the timer when the marker found status is received; calculating at the deskew modules, a compensated delay for each of the data lanes based on the saved timer value and a number of pipeline stages associated with the data lane, wherein calculating said compensated delay for a local lane comprises subtracting the number of pipeline stages for the local lane from each of said incoming marker found timer values and identifying a maximum compensated delay; and setting at the deskew modules, an entry point to each of the dynamic entry shift registers based on said maximum compensated delay to deskew data between the data lanes, said maximum compensated delay representing a skew between the local lane and a lane that received the marker last; wherein at least two of the data lanes are physically separated from one another on the die.

19 . The method of claim 18 wherein receiving data at a die comprises receiving data at remote portions of a die.

20 . The method of claim 18 wherein receiving data at a die comprises receiving data at two die comprising the data lanes on a chip-to-chip interface.

Assignees

• Cisco Tech Inc

Inventors

• Lawson Matthew Todd
• Butler Ii Lewis Leo
• Bussa Rajashekar Reddy

Classifications

• G06F13/20 Primary

  for access to input/output bus · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title