Apparatuses and methods for in-memory operations

Patent metadata

Field	Value
Publication number	US-2019115063-A1
Application number	US-201816218876-A
Country	US
Kind code	A1
Filing date	Dec 13, 2018
Priority date	Feb 22, 2017
Publication date	Apr 18, 2019
Grant date	—

Abstract

The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes sensing circuitry coupled to the first subset, the sensing circuitry including a sense amplifier and a compute component. The apparatus also includes a controller configured to direct a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset and performance of a sequential plurality of operations in-memory on the number of data values by the first sensing circuitry coupled to the first subset.

First claim

What is claimed is:

1 . An apparatus, comprising:
a memory device comprising a plurality of subarrays of memory cells, the plurality of subarrays including a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays; and a controller configured to direct:
a first movement of a number of data values from a subarray in the second subset to a subarray in the first subset; and
performance of a sequential plurality of operations in-memory on the number of data values, wherein the number of data values are stored by a sense amplifier and a compute component in first sensing circuitry coupled to the first subset until the performance of the sequential plurality of operations is completed.

2 . The apparatus of claim 1 , wherein the controller is further configured to direct:
a second movement of a data value from the subarray in the first subset to a sub array in the second subset; wherein the data value is a result of the sequential plurality of operations performed on the number of data values moved from the subarray in the second subset.

3 . The apparatus of claim 1 , wherein results of each of the respective sequential plurality of operations are stored by the subarray in the first subset until the performance of the sequential plurality of operations is completed to compute a result of a last of the sequential plurality of operations.

4 . The apparatus of claim 1 , wherein results of each of the respective sequential plurality of operations are stored by the first sensing circuitry coupled to the first subset until the performance of the sequential plurality of operations is completed to compute a result of a last of the sequential plurality of operations.

5 . The apparatus of claim 1 , wherein the memory device further comprises:
second sensing circuitry coupled to the second subset; wherein:
the second sensing circuitry includes a sense amplifier and no compute component; and
the second subset stores the number of data values on which the sequential plurality of operations will be performed by the first sensing circuitry as a number of sensed data values in the second sensing circuitry prior to the first movement of the number of data values.

6 . The apparatus of claim 1 , wherein a subarray in the second subset stores a result data value, on which the sequential plurality of operations has been performed by the first sensing circuitry, subsequent to a second movement of the data value.

7 . The apparatus of claim 1 , wherein a subarray in the first subset stores a result data value, on which the sequential plurality of operations has been performed by the first sensing circuitry, subsequent to a second movement of the data value.

8 . A system, comprising:
a controller coupled to a memory device, wherein the memory device comprises:
a first subset of a plurality of sub arrays of memory cells;
a second subset of the plurality of subarrays of memory cells;
sensing circuitry coupled to the first and second subsets, the sensing circuitry including a sense amplifier and a compute component coupled to a respective sense line of a plurality of sense lines for the first subset; and
responsive to receipt from a host of instructions to perform a sequential plurality of operations, the controller is configured to direct:
performance of the sequential plurality of operations in-memory on the number of data values in the sensing circuitry of the selected subarray in the first subset; and
movement of a data value, resulting from the performance of the sequential plurality of operations, from the sensing circuitry to a selected destination;
wherein the selected destination comprises selection from each of a selected row in a selected subarray of the first subset, a selected row in a selected subarray of the second subset, and a selected row in a selected vector register separate from the plurality of subarrays and coupled to the controller.

9 . The system of claim 8 , wherein the memory device further comprises:
an I/O line shared by the sensing circuitry of a selected subarray of the first subset and the sensing circuitry of a selected subarray of the second subset, and the selected vector register; wherein: the shared I/O line is configured to selectably couple to the sensing circuitry of the first subset to enable movement of a number of result data values stored in the first subset to the selected destination; and the selected destination comprises the selected row in the selected subarray of the second subset and the selected row in a selected vector register.

10 . The system of claim 8 , wherein the memory device further comprises:
a number of vector registers selectably coupled to the controller; an I/O line shared by the sensing circuitry of the selected subarray of the first subset and the sensing circuitry of the selected subarray of the second subset, the selected vector register, and a selected bank register separate from the plurality of subarrays and coupled to the controller; wherein: the shared I/O line is configured to selectably couple to the sensing circuitry of the first subset to enable movement of a number of result data values stored in the first subset to the selected destination; and the selected destination comprises the selected row in the selected subarray of the second subset, the selected row in the selected bank register, and the selected row in the selected vector register.

11 . The system of claim 8 , wherein the controller comprises:
a microcode engine configured to execute a set of instructions to direct:
movement of a number of data values from a corresponding number of memory cells selected from a source row in the first subset or the second subset of the plurality of subarrays to a corresponding number of memory cells in a selected row in a selected bank register and the selected row in the selected vector register.

12 . The system of claim 11 , wherein the microcode engine is further configured to execute the set of instructions to:
selectably direct storage of a data value in the selected subarray in the second subset, the selected row in the selected bank register, and the selected row in the vector register; wherein the storage of the respective data value is selectably offset a number of memory cells in the selected destination relative to storage of the respective data value in a memory cell in a source row of the first subset.

13 . The system of claim 12 , wherein a first number of memory cells in the selected source row in the first subset differs from a second number of memory cells in at least one of the source row in the second subset, the selected row in the selected bank register, and the selected row in the selected vector register.

14 . The system of claim 8 , wherein the memory device further comprises:
connection circuitry configured to connect sensing circuitry coupled to a particular column in a number of subarrays in the second subset to a number of rows in a corresponding column in a first subarray in the first subset; and a microcode engine configured to execute a set of instructions to direct:
the connection circuitry to move a plurality of data values from the number of subarrays in the second subset to a corresponding plurality of selected rows and the corresponding column in the first subarray in the first subset for performance of the sequential plurality of operations;
the plurality of selected rows and the corresponding column in the first subarray in the first subset is configured to receive the plurality of data values; and
the controller directs the perfo

Assignees

• Micron Technology Inc

Inventors

• Lea Perry V

Classifications

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/061 Primary

  Improving I/O performance · CPC title