Semiconductor Die Attach System and Method

Patent metadata

Field	Value
Publication number	US-2019109112-A1
Application number	US-201715725796-A
Country	US
Kind code	A1
Filing date	Oct 5, 2017
Priority date	Oct 5, 2017
Publication date	Apr 11, 2019
Grant date	—

Abstract

A semiconductor package includes a semiconductor die, a substrate for supporting the semiconductor die, an encapsulant covering the semiconductor die and at least part of the substrate, and a die attach material attaching the semiconductor die to the substrate. The die attach material includes molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant. A corresponding method of manufacturing the semiconductor package is also described.

First claim

What is claimed is:

1 . A semiconductor package, comprising:
a semiconductor die; a substrate for supporting the semiconductor die; an encapsulant covering the semiconductor die and at least part of the substrate; and a die attach material attaching the semiconductor die to the substrate, the die attach material comprising molecules having a first functional group with at least one free electron pair and a second functional group chemically reacted or reactable with the encapsulant in a way that promotes adhesion with the encapsulant.

2 . The semiconductor package of claim 1 , wherein the semiconductor die has a thickness in a range of 20 micrometers to 300 micrometers, and wherein the die attach material does not extend onto a main surface of the semiconductor die facing away from the substrate.

3 . The semiconductor package of claim 1 , wherein the semiconductor die has a thickness in a range of 50 micrometers to 150 micrometers, and wherein the die attach material does not extend onto a main surface of the semiconductor die facing away from the substrate.

4 . The semiconductor package of claim 1 , wherein the molecules are bis-amino molecules.

5 . The semiconductor package of claim 4 , wherein the bis-amino molecules comprise 1,6-diamino-hexane.

6 . The semiconductor package of claim 1 , wherein the molecules are bis-epoxy molecules.

7 . The semiconductor package of claim 6 , wherein the bis-epoxy molecules comprise 1,6-hexanediol diglycidyl ether.

8 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an epoxy group.

9 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an amine group.

10 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an amino acid group.

11 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is a silane group.

12 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is a sulfur group.

13 . The semiconductor package of claim 1 , wherein the second functional group of the molecules is an epoxy group.

14 . The semiconductor package of claim 1 , wherein the second functional group of the molecules is a glycidyl ether group.

15 . The semiconductor package of claim 1 , wherein the second functional group of the molecules is a silane group.

16 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an amino group and the second functional group is an epoxy group.

17 . The semiconductor package of claim 16 , wherein the molecules are 1-amino-6-hexaneol gylcidyl ether molecules.

18 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an amino group and the second functional group is silane group.

19 . The semiconductor package of claim 1 , wherein the first functional group of the molecules is an epoxy group and the second functional group is silane group.

20 . The semiconductor package of claim 1 , wherein the molecules have a cumulative percentage by weight in a range of 0.1 wt % to 20 wt %.

21 . The semiconductor package of claim 1 , wherein the die attach material comprises electrically and/or thermally conductive additives, and wherein the molecules have a cumulative percentage by weight of 2 wt % or less.

22 . The semiconductor package of claim 1 , wherein the die attach material is devoid of electrically and thermally conductive additives, and wherein the molecules have a cumulative percentage by weight of 10 wt % or less.

23 . The semiconductor package of claim 1 , further comprising a coating applied to the semiconductor die and contacting the encapsulant, wherein the coating comprises the same molecules as the die attach material in a way that promotes adhesion with the encapsulant.

24 . The semiconductor package of claim 1 , wherein the semiconductor die is a power transistor die.

25 . The semiconductor package of claim 1 , wherein the semiconductor die is a logic die, a sensor die, a memory die, a passive die, or power transistor die or a power diode die.

26 . A method of manufacturing a semiconductor package, the method comprising:
applying a die attach material to a substrate, the die attach material comprising molecules having a first functional group with at least one free electron pair and a second functional group; placing a semiconductor die on the die attach material; covering the semiconductor die and at least part of the substrate with an encapsulating material; and processing the substrate with the semiconductor die and the encapsulating material at an elevated temperature, to cure the encapsulating material, solidify the die attach material and chemically react the second functional group of at least some of the molecules with unreacted epoxy functional groups of the encapsulating material in a way that promotes adhesion with the encapsulating material as the encapsulating material cures.

27 . The method of claim 26 , wherein applying the die attach material to the substrate comprises one of:
applying an adhesive to a die attach surface of the substrate, the adhesive comprising the molecules; applying a solder paste to the die attach surface of the substrate, the solder paste comprising the molecules; applying a sinter paste to the die attach surface of the substrate, the sinter paste comprising the molecules; and applying a laminate film to the die attach surface of the substrate, the laminate film comprising the molecules.

28 . The method of claim 26 , wherein the die attach material comprises a solder, and wherein the solder with the molecules is applied to the substrate before covering the semiconductor die and at least part of the substrate with the encapsulating material.

29 . The method of claim 26 , further comprising:
applying a coating to the semiconductor die before covering the semiconductor die and at least part of the substrate with the encapsulating material, the coating comprising the same molecules as the die attach material, wherein the second functional group of at least some of the molecules of the coating chemically react with the precursor of the encapsulating material during the processing at the elevated temperature, in a way that promotes adhesion with the encapsulating material as the encapsulating material cures.

30 . The method of claim 26 , wherein the elevated temperature is in a range of 125° C. to 300° C.

31 . The method of claim 26 , wherein the elevated temperature is in a range of 150° C. to 200° C.

Assignees

• Infineon Technologies Ag

Inventors

• Mahler Joachim
• Meyer-Berg Georg

Classifications

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title