Method for manufacturing array substrate, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-2019103419-A1
Application number	US-201816028017-A
Country	US
Kind code	A1
Filing date	Jul 5, 2018
Priority date	Sep 29, 2017
Publication date	Apr 4, 2019
Grant date	—

Abstract

An array substrate, a manufacturing method thereof, and a display apparatus are provided. The array substrate includes a display area and a non-display area in the periphery of the display area, the display area includes pixel regions, the display and non-display areas are provided with via holes, wherein each pixel region is provided, at a side facing a display side, with a reflection layer configured to reflect light irradiated thereon from an external light source to form a display image; and an anti-deterioration layer in contact with the reflection layer is provided in the via holes in the display and non-display areas. Thus, by using a new material, utilization of external light source is improved without additional masking process, and connection in via holes in the display area, and especially in the non-display area is achieved, which prevents deterioration of the via holes and poor contact resistance.

First claim

1 . An array substrate, comprising a display area and a non-display area in the periphery of the display area, the display area comprising a plurality of pixel regions, both the display area and the non-display area being provided with via holes, wherein each of the plurality of pixel regions is provided with a reflection layer at a side facing a display side, and the reflection layer is configured to reflect light irradiated thereon from an external light source to form a display image; and
an anti-deterioration layer is provided in the via holes in the display area and the non-display area, and the anti-deterioration layer is in contact with the reflection layer.

2 . The array substrate of claim 1 , wherein in the display area, the anti-deterioration layer and the reflection layer have substantially the same pattern.

3 . The array substrate of claim 1 , wherein the anti-deterioration layer is made of any one or any combination of molybdenum, niobium, and molybdenum titanium alloy.

4 . The array substrate of claim 1 , wherein the reflection layer is made of any one or any combination of aluminum, silver, and aluminum neodymium alloy.

5 . The array substrate of claim 1 , wherein each of the plurality of pixel regions is provided with a substrate and a thin film transistor, the thin film transistor is on the substrate, and the anti-deterioration layer is on a side of the thin film transistor distal to the substrate, the reflection layer is on a side of the anti-deterioration layer distal to the thin film transistor, and the reflection layer and the anti-deterioration layer are coupled to a drain electrode of the thin film transistor.

6 . The array substrate of claim 5 , further comprising a transparent electrode layer coupled to the anti-deterioration layer and the reflection layer, wherein the transparent electrode layer is on a side of the anti-deterioration layer close to the thin film transistor.

7 . The array substrate of claim 6 , wherein the transparent electrode layer is further provided in the via holes of the display area and the non-display area.

8 . A method for manufacturing an array substrate, wherein the array substrate comprises a display area and a non-display area in the periphery of the display area, the display area comprises a plurality of pixel regions, the display area and the non-display area are both provided with via holes, and the method comprises: forming a reflection layer in each of the plurality of pixel regions, the reflection layer being configured to reflect light irradiated thereon from an external light source to form a display image; and forming an anti-deterioration layer in the via holes in the display area and the non-display area, the anti-deterioration layer being in contact with the reflection layer.

9 . The method of claim 8 , wherein the anti-deterioration layer and the reflection layer are formed in one patterning process, and in the display area, the anti-deterioration layer and the reflection layer have substantially the same pattern.

10 . The method of claim 9 , wherein each of the plurality of pixel regions further comprises a substrate and a thin film transistor, and the method comprises:
forming the thin film transistor on the substrate, wherein the anti-deterioration layer is provided on a side of the thin film transistor distal to the substrate, the reflection layer is provided on a side of the anti-deterioration layer distal to the thin film transistor, and the reflection layer and the anti-deterioration layer are coupled to a drain electrode of the thin film transistor.

11 . The method of claim 10 , wherein forming the anti-deterioration layer and the reflection layer in one patterning process comprises: sequentially depositing an anti-deterioration material layer and a reflection material layer, and performing one patterning process on the anti-deterioration material layer and the reflection material layer using a half tone mask or a gray tone mask to form a pattern comprising the anti-deterioration layer and the reflection layer, wherein blocking areas of the half tone mask or the gray tone mask correspond to the pixel regions and the via holes in the display area, half-exposing areas of the half tone mask or the gray tone mask correspond to the via holes in the non-display area, and fully-exposing areas of the half tone mask or the gray tone mask correspond to other areas.

12 . The method of claim 8 , wherein each of the plurality of pixel regions further comprises a substrate, a thin film transistor and a transparent electrode layer, and the method comprises:
forming the thin film transistor on the substrate; and forming the transparent electrode layer, the anti-deterioration layer and the reflection layer on a side of the thin film transistor distal to the substrate in one patterning process, wherein the transparent electrode layer is provided on a side of the thin film transistor distal to the substrate, the anti-deterioration layer is provided on a side of the transparent electrode layer distal to the thin film transistor, the reflection layer is provided on a side of the anti-deterioration layer distal to the transparent electrode layer, and the transparent electrode layer, the reflection layer and the anti-deterioration layer are coupled to a drain electrode of the thin film transistor.

13 . The method of claim 12 , wherein forming the transparent electrode layer, the anti-deterioration layer and the reflection layer in one patterning process comprises: sequentially depositing a transparent electrode material layer, an anti-deterioration material layer, and a reflection material layer, and performing one patterning process on the transparent electrode material layer, the anti-deterioration material layer and the reflection material layer using a half tone mask or a gray tone mask to form a pattern comprising the transparent electrode layer, the anti-deterioration layer and the reflection layer, wherein blocking areas of the half tone mask or the gray tone mask correspond to the pixel regions and the via holes in the display area, half-exposing areas of the half tone mask or the gray tone mask correspond to the via holes in the non-display area, and fully-exposing areas of the half tone mask or the gray tone mask correspond to other areas.

14 . A display apparatus, comprising the array substrate of claim 1 .

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Shoukun
• Guo Huibin
• Han Hao
• Fu Fangbin
• Song Yongzhi

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/133553

  Reflecting elements (associated to illuminating devices G02F1/133605) · CPC title

• G02F2203/02

  reflective · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• H01L27/1288

  Electricity · mapped topic