Semiconductor device

Patent metadata

Field	Value
Publication number	US-2019103340-A1
Application number	US-201816146340-A
Country	US
Kind code	A1
Filing date	Sep 28, 2018
Priority date	Oct 2, 2017
Publication date	Apr 4, 2019
Grant date	—

Abstract

A semiconductor device is provided with a first insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a first semiconductor element disposed on the metal layer on one face of the first insulated substrate, a second insulated substrate including an insulator layer and a metal layer disposed on each of two faces of the insulator layer, a second semiconductor element disposed on one of the metal layers of the second insulated substrate, and an encapsulant encapsulating the first semiconductor element and the second semiconductor element. The metal layer on the other face of the first insulated substrate and the metal layer on the other face of the second insulated substrate are exposed on a first flat surface of the encapsulant.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a first insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer; a first semiconductor element disposed on the metal layer on one face of the first insulated substrate; a second insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer; a second semiconductor element disposed on the metal layer on one face of the second insulated substrate; and an encapsulant encapsulating the first semiconductor element and the second semiconductor element, wherein the metal layer on the other face of the first insulated substrate and the metal layer on the other face of the second insulated substrate are exposed on a first flat surface of the encapsulant.

2 . The semiconductor device according to claim 1 , further comprising:
a third insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer; and a fourth insulated substrate comprising an insulator layer and a metal layer disposed on each of two faces of the insulator layer, wherein the third insulated substrate is opposed to the first insulated substrate across the first semiconductor element, the metal layer on one face of the third insulated substrate being electrically connected with the first semiconductor element, the fourth insulated substrate is opposed to the second insulated substrate across the second semiconductor element, the metal layer on one face of the fourth insulated substrate being electrically connected with the second semiconductor element, and wherein the metal layer on the other face of the third insulated substrate and the metal layer on the other face of the fourth insulated substrate are exposed on a second flat surface of the encapsulant, the second flat surface being located opposite to the first flat surface.

3 . The semiconductor device according to claim 2 , further comprising:
a first conductive spacer disposed between the first semiconductor element and the third insulated substrate; and a second conductive spacer disposed between the second semiconductor element and the fourth insulated substrate; wherein each of linear expansion coefficients of the first conductive spacer and the second conductive spacer is smaller than each of linear expansion coefficients of the metal layers of the first insulated substrate and the second insulated substrate and is smaller than a linear expansion coefficient of the encapsulant.

4 . The semiconductor device according to claim 3 , wherein
each of materials of the metal layers of the first insulated substrate and the second insulated substrate is copper, and each of materials of the first conductive spacer and the second conductive spacer is copper-molybdenum alloy or copper-tungsten alloy.

5 . The semiconductor device according to claim 1 , wherein the metal layer on the one face is greater in thickness than the metal layer on the other face in at least one of the first insulated substrate and the second insulated substrate.

6 . The semiconductor device according to claim 1 , wherein the metal layer on the other face is greater in thickness than the metal layer on the one face in at least one of the first insulated substrate and the second insulated substrate.

7 . The semiconductor device according to claim 1 , wherein the metal layer on the one face is equal in thickness with the metal layer on the other face in at least one of the first insulated substrate and the second insulated substrate.

8 . The semiconductor device according to claim 1 , at least one of the first insulated substrate and the second insulated substrate is a DBC (Direct Bonded Copper) substrate.

Assignees

• Toyota Motor Co Ltd

Inventors

• TSUCHIMOCHI Shingo

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title