Memory system

Patent metadata

Field	Value
Publication number	US-2019087266-A1
Application number	US-201815919809-A
Country	US
Kind code	A1
Filing date	Mar 13, 2018
Priority date	Sep 20, 2017
Publication date	Mar 21, 2019
Grant date	—

Abstract

According to one embodiment, a memory system includes a nonvolatile memory, an encoding part configured to generate a plurality of component codes including a first component code and a second component code different from the first component code, by using, as an information symbol, at least one symbol of a plurality of symbols included in user data to be written into the nonvolatile memory, and a memory interface configured to write the plurality of component codes into the nonvolatile memory. The encoding part includes a plurality of encoders each configured to generate a parity corresponding to each of the plurality of component codes, and a first distributor configured to divide a first symbol string of the user data into a plurality of chunks, each of which has a first symbol length smaller than that of the first symbol string, and to input each of the plurality of chunks generated by the division, into any one f at least different two of the plurality of encoders. The memory interface is configured to write the first symbol string and parities corresponding to the first symbol string into the nonvolatile memory.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory; an encoding part configured to generate a plurality of component codes including a first component code and a second component code different from the first component code, by using, as an information symbol, at least one symbol of a plurality of symbols included in user data to be written into the nonvolatile memory; and a memory interface configured to write the plurality of component codes into the nonvolatile memory, wherein the encoding part includes
a plurality of encoders each configured to generate a parity corresponding to each of the plurality of component codes, and
a first distributor configured to divide a first symbol string of the user data into a plurality of chunks, each of which has a first symbol length smaller than that of the first symbol string, and to input each of the plurality of chunks generated by the division, into any one of at least different two of the plurality of encoders, and
wherein the memory interface is configured to write the first symbol string and parities corresponding to the first symbol string into the nonvolatile memory.

2 . The memory system according to claim 1 , wherein
the first component code is a component code of a first dimension, the second component code is a component code of a second dimension different from the first dimension, the plurality of encoders includes one or more first encoders each configured to generate a parity of a component code of the first dimension, and one or more second encoders each configured to generate a parity of a component code of the second dimension, and the first distributor is configured to input each of the chunks into any one of the one or more first encoder and into any one of the one or more second encoders.

3 . The memory system according to claim 1 , wherein
combinations of at least two component codes among the plurality of component codes include one or more effective combinations each of which multiply protects at least one symbol in the first symbol string, and one or more ineffective combinations each of which does not multiply protect a symbol in the first symbol string, and when a number of chunks is equal to or smaller than a number of the effective combinations, the first distributor determines combinations of encoders to serve as respective input destinations for the plurality of chunks, such that a combination of encoders for the component codes, into which one chunk of the plurality of chunks is to be input, does not overlap with a combination of encoders for the component codes, into which another chunk is to be input.

4 . The memory system according to claim 1 , wherein
combinations of at least two component codes among the plurality of component codes include one or more effective combinations each of which multiply protects at least one symbol in the first symbol string, and one or more ineffective combinations each of which does not multiply protect a symbol in the first symbol string, and when a number of chunks is larger than a number of the effective combinations, the first distributor allocates input destinations for some chunks of the plurality of chunks to respective ones of all the effective combinations, and then determines input destinations for rest of the chunks from combinations overlapping with combinations which input destinations have already been allocated.

5 . The memory system according to claim 3 , wherein
when the number of chunks is larger than the number of the effective combinations, the first distributor determines combinations of encoders to serve as respective input destinations for the plurality of chunks, such that a difference between numbers of chunks to be input into the respective effective combinations is equal to or smaller than a predetermined threshold.

6 . The memory system according to claim 2 , wherein, when a number of chunks is larger than a number of encoders for component codes of the first dimension, the first distributor determines encoders for component codes of the first dimension to serve as respective input destinations for the plurality of chunks, such that a difference between numbers of chunks to be input into the respective encoders for component codes of the first dimension is equal to or smaller than a predetermined threshold.

7 . The memory system according to claim 2 , wherein, when a number of chunks is larger than a number of encoders for component codes of the second dimension, the first distributor determines encoders for component codes of the second dimension to serve as respective input destinations for the plurality of chunks, such that a difference between numbers of chunks to be input into the respective encoders for component codes of the second dimension is equal to or smaller than a predetermined threshold.

8 . The memory system according to claim 2 , wherein
the first distributor includes
a first cyclic selector configured to input each of the plurality of chunks into any one of the encoders for component codes of the first dimension, in order in accordance with an arrangement of the first symbol string,
a second cyclic selector configured to input each of the plurality of chunks into any one of the encoders for component codes of the second dimension, in order in accordance with an arrangement of the first symbol string,
the first distributor is configured to set the first cyclic selector with a first period including a number of cycles in a same number as a number of component codes of the first dimension, and to set the second cyclic selector with a second period including a number of cycles in a same number as a number of component codes of the second dimension, the first cyclic selector is configured to input in a dispersed state the plurality of chunks into some of the first encoders in a same number as the number of cycles of the first period, and the second cyclic selector is configured to input in a dispersed state the plurality of chunks into some of the second encoders in a same number as the number of cycles of the second period.

9 . The memory system according to claim 2 , wherein
the first distributor further includes a selector configured to receive input of the plurality of chunks and respective parities of the plurality of component codes, and the selector is configured to calculate a parity of a third component code of the plurality of component codes, and then to input the parity of the third component code into an encoder for a fourth component code, a parity of which has not yet been calculated.

10 . The memory system according to claim 1 , wherein the first distributor is configured to receive input of the user data in units of a second symbol string that has a second symbol length equal to or larger than the first symbol length and smaller than that of the first symbol string, and to divide the second symbol string into one or more chunks.

11 . The memory system according to claim 1 , comprising:
a first syndrome calculator configured to calculate first syndrome of the first component code; a second syndrome calculator configured to calculate a second syndrome of the second component code; a second distributor configured to divide a third symbol string read from the nonvolatile memory by the memory interface into a plurality of chunks, each of which has the first symbol length as in the first distributor, and to input chunks corresponding to user data to be read and chunks corresponding to parities of a first dimension, of the plurality of chunks generated by the division, into the first syndrome calculator, and input the chunks corresponding to the user data to be read

Assignees

• Toshiba Memory Corp

Inventors

• Watanabe Daiki
• Lin Yuchieh

Classifications

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/2909

  Product codes · CPC title

• H03M13/6516

  Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields · CPC title