Vertical field effect transistor and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-2019081174-A1
Application number	US-201816044584-A
Country	US
Kind code	A1
Filing date	Jul 25, 2018
Priority date	Sep 11, 2017
Publication date	Mar 14, 2019
Grant date	—

Abstract

A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

First claim

What is claimed is:

1 . A field effect transistor (vFET), comprising:
a first impurity region doped with first impurities at an upper portion of a substrate; a first diffusion control pattern on the first impurity region, the first diffusion control pattern being configured to control the diffusion of the first impurities; a channel extending in a vertical direction on the first diffusion control pattern, the vertical direction substantially orthogonal to an upper surface of the substrate; a second impurity region doped with second impurities on the channel; a second diffusion control pattern between the channel and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities; and a gate structure adjacent to the channel.

2 . The vFET of claim 1 , wherein the first diffusion control pattern includes silicon-germanium.

3 . The vFET of claim 1 , wherein a lower portion of the first diffusion control pattern includes the first impurities.

4 . The vFET of claim 1 , wherein the second diffusion control pattern includes silicon-germanium.

5 . The vFET of claim 4 , wherein at least an upper portion of the second diffusion control pattern includes the second impurities.

6 . The vFET of claim 1 , further comprising:
a first electrode on the second impurity region; and a second electrode on the first impurity region, the second electrode being spaced apart from the gate structure.

7 . The vFET of claim 6 , wherein a central upper portion of the second impurity region has a sharp upper surface, and
wherein the vFET further comprises a metal silicide pattern between the second impurity region and the first electrode, the metal silicide pattern covering the upper surface of the second impurity region.

8 . The vFET of claim 6 , wherein top surfaces of the first and second electrodes are substantially coplanar with each other.

9 . The vFET of claim 1 , further comprising a spacer under the gate structure, the spacer covering a lower portion of the channel.

10 . The vFET of claim 9 , wherein the spacer includes:
a first pattern covering a lower sidewall of the channel and including silicon oxide; and a second pattern conformally disposed on the first pattern, the second pattern including silicon nitride.

11 . The vFET of claim 1 , wherein the gate structure includes:
a gate insulation pattern disposed on a central sidewall of the channel and including a high-k dielectric material; and a gate electrode on the gate insulation pattern, the gate electrode including a metal.

12 . A semiconductor device, comprising:
a first impurity region doped with first impurities at an upper portion of a substrate; a first diffusion control pattern on the first impurity region, the first diffusion control pattern being configured to control the diffusion of the first impurities; channels spaced apart from each other on the first diffusion control pattern along a direction parallel to an upper surface of the substrate, each of the channels extending in a vertical direction substantially orthogonal to the upper surface of the substrate; a second impurity region doped with second impurities positioned above the channels; a second diffusion control pattern between each of the channels and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities; and gate structures adjacent to the channels.

13 . The semiconductor device of claim 12 , wherein the gate structures are connected with each other to form a single gate structure.

14 . The semiconductor device of claim 12 , wherein the first diffusion control pattern includes protrusions spaced apart from each other, and
wherein the channels are formed on the respective protrusions of the first diffusion control pattern.

15 . The semiconductor device of claim 14 , further comprising a spacer positioned on lower portions of the channels and the protrusions of the first diffusion control pattern.

16 . The semiconductor device of claim 12 , wherein the second impurity region has an uneven upper surface, and
wherein the semiconductor device further comprises: a metal silicide pattern covering the upper surface of the second impurity region; a first electrode on the metal silicide pattern; and a second electrode on the first impurity region, the second electrode being spaced apart from the gate structures.

17 . A semiconductor device, comprising:
first diffusion control patterns spaced apart from each other on a substrate; first impurity regions doped with first impurities at upper portions of the substrate below the first diffusion control patterns; channels on the first diffusion control patterns, each of the channels extending in a vertical direction substantially orthogonal to an upper surface of the substrate; a second impurity region doped with second impurities positioned above the channels; a second diffusion control pattern between each of the channels and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities; and gate structures adjacent to the channels.

18 . The semiconductor device of claim 17 , further comprising spacers positioned above the first impurity regions, the spacers positioned on lower portions of the channels.

19 . The semiconductor device of claim 18 , wherein the spacers are positioned on lower portions of the first diffusion control patterns.

20 . The semiconductor device of claim 19 , wherein gate structures are connected with each other to form a single gate structure.

Assignees

• Samsung Electronics Co Ltd

Inventors

• You Jung-Gun
• Kim Chang-Hee
• Park Sung-Ii
• Lee Dong-Hun

Classifications

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/693

  characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H01L21/3083

  Electricity · mapped topic

• H01L29/4232

  Electricity · mapped topic