Array substrate, method for manufacturing the same, and display device

US2019072829A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019072829-A1
Application numberUS-201816121968-A
CountryUS
Kind codeA1
Filing dateSep 5, 2018
Priority dateSep 6, 2017
Publication dateMar 7, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven.

First claim

Opening claim text (preview).

What is claimed is: 1 . An array substrate, comprising a base substrate, gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, wherein a surface of the diffuse reflection layer facing a light emitting side of the array substrate is uneven. 2 . The array substrate of claim 1 , further comprising a light shielding layer for sheltering a thin film transistor of the array substrate from backlight. 3 . The array substrate of claim 2 , wherein the diffuse reflection layer and the light shielding layer are arranged on a same layer and made of a same material. 4 . The array substrate of claim 1 , wherein an orthogonal projection of the diffuse reflection layer onto the base substrate at least partially overlaps an orthogonal projection of a corresponding one of the plurality of pixel regions onto the base substrate. 5 . The array substrate of claim 4 , wherein the array substrate is an array substrate of a liquid crystal display device. 6 . The array substrate of claim 1 , further comprising an insulating layer arranged on the base substrate, wherein the insulating layer is arranged on a side of the diffuse reflection layer proximate to the base substrate, and a surface of the insulating layer facing a side of the diffuse reflection layer is uneven. 7 . The array substrate of claim 1 , wherein a material of the diffuse reflection layer comprises at least one of Ag, Au, Mo, Al, and Cu. 8 . The array substrate of claim 1 , wherein the diffuse reflection layer comprises at least one of a plate-type structure, a strip-type structure, and a block-type structure comprising blocks arranged in a matrix form. 9 . A method for manufacturing the array substrate of claim 1 , comprising: forming the diffuse reflection layer in the plurality of pixel regions, wherein the surface of the diffuse reflection layer facing the light emitting side of the array substrate is uneven. 10 . The method of claim 9 , wherein the forming the diffuse reflection layer in the plurality of pixel regions comprises: forming a metal film layer; forming a photoresist layer on the metal film layer; exposing and developing the photoresist layer, to form a photoresist layer pattern, wherein the photoresist layer pattern comprises at least a first pattern region corresponding to a region where the diffuse reflection layer is arranged; removing the metal film layer not covered by the photoresist layer pattern, to form a metal film layer pattern; bombarding the photoresist layer pattern through a plasma process to ash the photoresist layer pattern, and continuing to bombard the metal film layer pattern so as to provide the metal film layer pattern with an uneven surface, wherein the metal film layer pattern comprises a pattern of the diffuse reflection layer; and stripping off the remaining photoresist layer. 11 . The method of claim 9 , wherein prior to forming the diffuse reflection layer in the plurality of pixel regions, the method further comprises: forming an insulating layer; and bombarding the insulating layer through a plasma process, to form an insulating layer having an uneven surface, wherein the forming the diffuse reflection layer in the plurality of pixel regions comprises: forming a metal film layer; forming a photoresist layer on the metal film layer; exposing and developing the photoresist layer, to form a photoresist layer pattern, wherein the photoresist layer pattern comprises at least a first pattern region corresponding to a region where the diffuse reflection layer is arranged; removing the metal film layer not covered by the photoresist layer pattern, to form a metal film layer pattern having an uneven surface, wherein the metal film layer pattern comprises a pattern of the diffuse reflection layer; and stripping off the remaining photoresist layer. 12 . The method of claim 10 , wherein the plasma process is a plasma descum process. 13 . The method of claim 11 , wherein the plasma process is a plasma descum process. 14 . The method of claim 10 , wherein the photoresist layer pattern further comprises a second pattern region corresponding to a region wherein a light shielding layer for sheltering a thin film transistor of the array substrate from backlight is arranged, and the formed metal film layer pattern further comprises a pattern of the light shielding layer. 15 . The method of claim 11 , wherein the photoresist layer pattern further comprises a second pattern region corresponding to a region wherein a light shielding layer for sheltering a thin film transistor of the array substrate from backlight is arranged, and the formed metal film layer pattern further comprises a pattern of the light shielding layer. 16 . The method of claim 9 , wherein an orthogonal projection of the diffuse reflection layer onto the base substrate at least partially overlaps an orthogonal projection of a corresponding one of the plurality of pixel regions onto the base substrate. 17 . The method of claim 9 , wherein a material of the metal film layer comprises at least one of Ag, Au, Mo, Al, and Cu. 18 . A display device, comprising the array substrate of claim 1 . 19 . The display device of claim 18 , wherein the array substrate further comprises a light shielding layer for sheltering a thin film transistor of the array substrate from backlight, and the diffuse reflection layer and the light shielding layer are arranged on a same layer and made of a same material. 20 . The display device of claim 18 , wherein the array substrate further comprises an insulating layer arranged on the base substrate, the insulating layer is arranged on a side of the diffuse reflection layer proximate to the base substrate, and a surface of the insulating layer facing a side of the diffuse reflection layer is uneven.

Assignees

Inventors

Classifications

  • by liquid etching only · CPC title

  • using masks for conductive or resistive materials · CPC title

  • Photolithographic processes · CPC title

  • Reflecting elements (associated to illuminating devices G02F1/133605) · CPC title

  • Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

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What does patent US2019072829A1 cover?
The present disclosure provides an array substrate, a method for manufacturing the same, and a display device. The array substrate includes a base substrate, and gate lines and data lines arranged on the base substrate to define a plurality of pixel regions, and a diffuse reflection layer arranged in the plurality of pixel regions, in which a surface of the diffuse reflection layer facing a lig…
Who is the assignee on this patent?
Boe Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/136209. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Mar 07 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).