Semiconductor device, signal processing system, and signal processing method

Patent metadata

Field	Value
Publication number	US-2019068211-A1
Application number	US-201816022190-A
Country	US
Kind code	A1
Filing date	Jun 28, 2018
Priority date	Aug 30, 2017
Publication date	Feb 28, 2019
Grant date	—

Abstract

A semiconductor device, a signal processing system, and a signal processing method are provided that regulate a change of characteristics in the event of aged deterioration. The semiconductor device of the present invention includes a reference voltage generation circuit that generates a reference voltage, an analog signal processing circuit that outputs a first processing signal according to the reference voltage, a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal, an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates the output of the analog signal processing circuit in response to the regulation signal.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a reference voltage generation circuit that generates a reference voltage; an analog signal processing circuit that outputs a first processing signal according to the reference voltage; a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal; an input section that receives a regulation signal for the outputted test signal, and a regulator circuit that regulates an output of the analog signal processing circuit in response to the regulation signal.

2 . The semiconductor device according to claim 1 ,
wherein the analog signal processing circuit is a circuit including an amplifier, and wherein the regulator circuit regulates a voltage of an input signal to the amplifier.

3 . The semiconductor device according to claim 1 ,
wherein the regulator circuit regulates the output of the analog signal processing circuit by regulating the reference voltage.

4 . The semiconductor device according to claim 3 ,
wherein the test signal output section outputs, as the test signal, one of the second processing signal and the reference voltage.

5 . The semiconductor device according to claim 1 ,
wherein the test signal output section receives an instruction for outputting the test signal from outside and then outputs the test signal in response to the instruction.

6 . The semiconductor device according to claim 1 , further comprising an instruction section that instructs the test signal output section to output the test signal if a driving time of the analog signal processing circuit reaches a predetermined time.

7 . The semiconductor device according to claim 1 , further comprising a memory section for storing the regulation signal,
the regulator circuit regulating the output of the analog signal processing circuit in response to the regulation signal stored in the memory section.

8 . The semiconductor device according to claim 1 , further comprising a switching circuit that repeatedly performs a switching operation.

9 . A signal processing system comprising:
a first semiconductor device including: a reference voltage generation circuit that generates a reference voltage; an analog signal processing circuit that outputs a first processing signal according to the reference voltage; a test signal output section that outputs, as a test signal, a second processing signal having a lower voltage than the first processing signal; an input section that receives a regulation signal for the outputted test signal; and a regulator circuit that regulates an output of the analog signal processing circuit in response to the regulation signal, and a second semiconductor device including: an AD converter circuit that converts, into a digital signal, the test signal outputted from the first semiconductor device and then outputs the digital signal, and a test circuit that compares the digital signal and a stored expected value and then outputs the regulation signal according to a difference value obtained as a comparison result.

10 . The signal processing system according to claim 9 ,
wherein the analog signal processing circuit is a circuit including an amplifier, and wherein the regulator circuit regulates a voltage of an input signal to the amplifier.

11 . The signal processing system according to claim 9 ,
wherein the regulator circuit regulates the output of the analog signal processing circuit by regulating the reference voltage.

12 . The signal processing system according to claim 11 ,
wherein the test signal output section outputs, as the test signal, one of the second processing signal and the reference voltage.

13 . The signal processing system according to claim 9 ,
wherein if a driving time of the analog signal processing circuit reaches a predetermined time, the test signal output section outputs the test signal, the AD converter circuit converts the test signal into the digital signal and outputs the digital signal, the test circuit compares the digital signal and the expected value and outputs the regulation signal, and the regulator circuit regulates the output of the analog signal processing circuit in response to the regulation signal.

14 . The signal processing system according to claim 9 ,
wherein if the difference value is larger than a predetermined value, until the difference value falls below the predetermined value, the regulator circuit repeatedly regulates the output of the analog signal processing circuit, the test signal output section repeatedly outputs the test signal, the AD converter circuit repeatedly converts the test signal into the digital signal and outputs the digital signal, and the test circuit repeatedly compares the digital signal and the expected value.

15 . The signal processing system according to claim 9 ,
wherein the second semiconductor device further includes a memory section for storing the regulation signal to be outputted to the first semiconductor device.

16 . The signal processing system according to claim 9 ,
wherein the first semiconductor device further includes a memory section for storing the regulation signal to be outputted to the regulator circuit.

17 . The signal processing system according to claim 9 ,
wherein the first semiconductor device further includes a memory section for storing the regulation signal to be outputted to the regulator circuit, and wherein the second semiconductor device further includes a memory section for storing the regulation signal to be outputted to the first semiconductor device.

18 . The signal processing system according to claim 9 ,
wherein the first semiconductor device further includes a switching circuit that repeatedly performs a switching operation.

19 . A signal processing method comprising the steps of:
generating a reference voltage by a first semiconductor device; outputting a first processing signal as an output of an analog signal processing circuit according to the reference voltage by the first semiconductor device; outputting a second processing signal having a lower voltage than the first processing signal, as a test signal by the first semiconductor device; converting the test signal into a digital signal and then outputting the digital signal by a second semiconductor device; comparing the digital signal and a stored expected value and then outputting a regulation signal by a second semiconductor device according to a difference value obtained as a comparison result; receiving the regulation signal by the first semiconductor device; and regulating the output of the analog signal processing circuit by the first semiconductor device in response to the regulation signal.

20 . The signal processing method according to claim 19 ,
wherein the analog signal processing circuit is a circuit including an amplifier, and wherein a voltage of an input signal to the amplifier is regulated in the step of regulating the output of the analog signal processing circuit.

Assignees

• Renesas Electronics Corp

Inventors

• Kodama Hiroto
• Kudo Masaki
• Kusunoki Takeshi

Classifications

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03M1/1071 Primary

  Measuring or testing · CPC title

• H03M1/0621 Primary

  with auxiliary conversion of a value corresponding to the physical parameter(s) to be compensated for · CPC title

• H03M1/183 Primary

  the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter · CPC title

• H03M1/1028

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title