Semiconductor device and image recognition system

Patent metadata

Field	Value
Publication number	US-2019065947-A1
Application number	US-201816035010-A
Country	US
Kind code	A1
Filing date	Jul 13, 2018
Priority date	Aug 25, 2017
Publication date	Feb 28, 2019
Grant date	—

Abstract

A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N. The product calculation circuit can calculate data of N×N all at once.

First claim

What is claimed is:

1 . A semiconductor device comprising:
an image recognition device having a convolution arithmetic processing circuit, wherein the convolution arithmetic processing circuit includes
a coefficient register where coefficients of an integration coefficient table are set,
a product calculation circuit that calculates products of an input image and the coefficients,
a channel register where a channel number of the integration coefficient table is set,
a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and
a plurality of output registers that store a result of the cumulative addition arithmetic operation,
wherein the integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N, and wherein the product calculation circuit can calculate data of N×N all at once.

2 . The semiconductor device according to claim 1 ,
wherein the channel selection circuit includes
a cumulative addition circuit that adds the products for each channel number, and
a cumulative addition register that holds an output of the cumulative addition circuit for each channel number, and
wherein the cumulative addition circuit performs the addition for each channel number in parallel.

3 . The semiconductor device according to claim 2 ,
wherein the channel selection circuit further includes a selector that outputs the output of the cumulative addition circuit to anyone of the output registers on the basis of the channel number.

4 . The semiconductor device according to claim 1 ,
wherein in each element of the integration coefficient table, a coefficient having a largest value among coefficients in each corresponding element in the input coefficient tables is stored.

5 . The semiconductor device according to claim 1 ,
wherein the number of the input coefficient tables is N and each of the input coefficient tables has a size of N×N.

6 . The semiconductor device according to claim 1 , further comprising:
an input pattern register; and an input pattern generation circuit that changes an arrangement of an input image based on content of the input pattern register, wherein the integration coefficient table is a table where L input coefficient tables are integrated, the integration coefficient table has a size of N×N, each of the L input coefficient tables has a size of M×M, and M is a value smaller than N, and wherein the product calculation circuit can calculate data of N×N all at once.

7 . The semiconductor device according to claim 6 ,
wherein the channel selection circuit includes
a cumulative addition circuit that adds the products for each channel number, and
a cumulative addition register that holds an output of the cumulative addition circuit for each channel number, and
wherein the cumulative addition circuit performs the addition for each channel number in parallel.

8 . The semiconductor device according to claim 7 ,
wherein the channel selection circuit further includes a selector that outputs the output of the cumulative addition circuit to anyone of the output registers on the basis of the channel number.

9 . The semiconductor device according to claim 6 ,
wherein the input pattern generation circuit repeats an input image of M×M L times and converts the L input images of M×M into an input image of N×N.

10 . An image recognition system comprising:
a semiconductor device; and a semiconductor storage device, wherein the semiconductor device includes
a convolution arithmetic processing circuit including a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image read from the semiconductor storage device and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation, and
a pooling circuit,
wherein the product calculation circuit can calculate data of N×N all at once, and wherein the integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N×N.

11 . The image recognition system according to claim 10 ,
wherein the channel selection circuit includes
a cumulative addition circuit that adds the products for each channel number, and
a cumulative addition register that holds an output of the cumulative addition circuit for each channel number, and
wherein the cumulative addition circuit performs the addition for each channel number in parallel.

12 . The image recognition system according to claim 11 ,
wherein the channel selection circuit further includes a selector that outputs the output of the cumulative addition circuit to anyone of the output registers on the basis of the channel number.

13 . he image recognition system according to claim 10 ,
wherein in each element of the integration coefficient table, a coefficient having a largest value among coefficients in each corresponding element in the input coefficient tables is stored.

14 . he image recognition system according to claim 10 ,
wherein the number of the input coefficient tables is N and each of the input coefficient tables has a size of N×N.

15 . The image recognition system according to claim 10 ,
wherein the semiconductor device further includes
an input pattern register, and
an input pattern generation circuit that changes an arrangement of an input image based on content of the input pattern register,
wherein the integration coefficient table is a table where L input coefficient tables are integrated, the integration coefficient table has a size of N×N, each of the L input coefficient tables has a size of M×M, and M is a value smaller than N, and wherein the product calculation circuit can calculate data of N×N all at once.

16 . The image recognition system according to claim 15 ,
wherein the channel selection circuit includes
a cumulative addition circuit that adds the products for each channel number, and
a cumulative addition register that holds an output of the cumulative addition circuit for each channel number, and
wherein the cumulative addition circuit performs the addition for each channel number in parallel.

17 . The image recognition system according to claim 16 ,
wherein the channel selection circuit further includes a selector that outputs the output of the cumulative addition circuit to anyone of the output registers on the basis of the channel number.

18 . The image recognition system according to claim 15 ,
wherein the input pattern generation circuit repeats an input image of M×M L times and converts the L input images of M×M into an input image of N×N.

Assignees

• Renesas Electronics Corp

Inventors

• Nakamura Atsushi
• UTAGAWA Akira
• Matsuo Shigeru

Classifications

• G06N3/045

  Combinations of networks · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T7/0002

  Inspection of images, e.g. flaw detection · CPC title

• G06N3/063 Primary

  using electronic means · CPC title

• G06N3/08 Primary

  Learning methods · CPC title