Technologies for providing efficient access to pooled accelerator devices

Patent metadata

Field	Value
Publication number	US-2019065083-A1
Application number	US-201715858557-A
Country	US
Kind code	A1
Filing date	Dec 29, 2017
Priority date	Aug 30, 2017
Publication date	Feb 28, 2019
Grant date	—

Abstract

Technologies for providing efficient access to pooled accelerator devices include an accelerator sled. The accelerator sled includes an accelerator device and a controller connected to the accelerator device. The controller is to provide, to a compute sled, accelerator abstraction data. The accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region. The controller is further to receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode. Additionally, the controller is to convert the request from a first format to a second format that is different from the second format and is usable by the accelerator device to perform the operation. Additionally, the controller is to perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode. Other embodiments are also described and claimed.

First claim

1 . An accelerator sled comprising:
an accelerator device; a controller connected to the accelerator device, wherein the controller is to (i) provide, to a compute sled, accelerator abstraction data, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region, (ii) receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode, (iii) convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation, and (iv) perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.

2 . The accelerator sled of claim 1 , wherein to perform the operation on the identified memory region comprises to perform the operation in a proxy mode.

3 . The accelerator sled of claim 2 , wherein to perform the operation in a proxy mode comprises to:
compare the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and perform, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.

4 . The accelerator sled of claim 3 , wherein to perform the requested operation comprises to perform the requested operation on an administrative command register.

5 . The accelerator sled of claim 3 , wherein to perform the requested operation comprises to reprogram the accelerator device or reset the accelerator device.

6 . The accelerator sled of claim 1 , wherein to perform the operation on the identified memory region of the accelerator device comprises to perform a direct access operation.

7 . The accelerator sled of claim 6 , wherein to perform the direct access operation comprises to enable the compute sled to write data to the identified memory region of the accelerator device.

8 . The accelerator sled of claim 6 , wherein to perform the direct access operation comprises to enable the compute sled to read data from the identified memory region of the accelerator device.

9 . The accelerator sled of claim 1 , wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and
wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.

10 . The accelerator sled of claim 1 , wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the accelerator device as multiple logical devices.

11 . The accelerator sled of claim 10 , wherein the accelerator device is a field programmable gate array with multiple slots and to provide the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises to provide accelerator abstraction data that represents each slot as a different logical device.

12 . The accelerator sled of claim 1 , wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled and the controller is further to identify the accelerator devices present on the sled and the memory regions of each accelerator device that are accessible by the compute sled.

13 . One or more machine-readable storage media comprising a plurality of instructions stored thereon that, in response to being executed, cause an accelerator sled to:
provide, to a compute sled, accelerator abstraction data, wherein the accelerator abstraction data represents the accelerator device as one or more logical devices, each logical device having one or more memory regions accessible by the compute sled, and defines an access mode usable to access each corresponding memory region; receive, from the compute sled, a request to perform an operation on an identified memory region of the accelerator device with a corresponding access mode; convert the request from a first format to a second format, wherein the first format is different from the second format and the second format is usable by the accelerator device to perform the operation; and perform, in response to the request, the operation on the identified memory region of the accelerator device with the corresponding access mode.

14 . The one or more machine-readable storage media of claim 13 , wherein to perform the operation on the identified memory region comprises to perform the operation in a proxy mode.

15 . The one or more machine-readable storage media of claim 14 , wherein to perform the operation in a proxy mode comprises to:
compare the requested operation to policy data indicative of whether one or more operations are allowed or disallowed; and perform, in response to a determination that the requested operation is allowed, the requested operation on the identified memory region of the accelerator device.

16 . The one or more machine-readable storage media of claim 15 , wherein to perform the requested operation comprises to perform the requested operation on an administrative command register.

17 . The one or more machine-readable storage media of claim 15 , wherein to perform the requested operation comprises to reprogram the accelerator device or reset the accelerator device.

18 . The one or more machine-readable storage media of claim 13 , wherein to perform the operation on the identified memory region of the accelerator device comprises to perform a direct access operation.

19 . The one or more machine-readable storage media of claim 18 , wherein to perform the direct access operation comprises to enable the compute sled to write data to the identified memory region of the accelerator device.

20 . The one or more machine-readable storage media of claim 18 , wherein to perform the direct access operation comprises to enable the compute sled to read data from the identified memory region of the accelerator device.

21 . The one or more machine-readable storage media of claim 13 , wherein the accelerator device is one of a plurality of accelerator devices on the accelerator sled; and
wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the plurality of accelerator devices as a single logical device.

22 . The one or more machine-readable storage media of claim 13 , wherein to provide the accelerator abstraction data comprises to provide accelerator abstraction data that represents the accelerator device as multiple logical devices.

23 . The one or more machine-readable storage media of claim 22 , wherein the accelerator device is a field programmable gate array with multiple slots and to provide the accelerator abstraction data that represents the accelerator device as multiple logical devices comprises to provide accelerator abstraction data that represents each slot as a different logical device.

24 . The one or more machine-readable storage media of claim 13 , wherein the accelerator device is one of a plurality of accelerator devices present on the accelerator sled and the plurality of i

Assignees

• Intel Corp

Inventors

• Sen Sujoy
• Balle Susanne M
• Ranganathan Narayan
• Custodio Evan
• Dormitzer Paul H
• Bernat Francesc Guim

Classifications

• G06F2201/86

  Event-based monitoring · CPC title

• G06F11/3006

  where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50) · CPC title

• G06F2201/885

  Monitoring specific for caches · CPC title

• G06F11/3442

  for planning or managing the needed capacity · CPC title

• G06F11/3466

  Performance evaluation by tracing or monitoring · CPC title