Sensor package structure

Patent metadata

Field	Value
Publication number	US-2019057992-A1
Application number	US-201715819741-A
Country	US
Kind code	A1
Filing date	Nov 21, 2017
Priority date	Aug 16, 2017
Publication date	Feb 21, 2019
Grant date	—

Abstract

A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically connected to the substrate and the sensor chip, a transparent layer facing the sensor chip, a support disposed on the substrate, and a packaging compound disposed on the substrate and covering side edges of the support and the transparent layer. A part of each wire is embedded in the support. A height from the upper surface of the substrate to the top of the support is larger than a height from the upper surface of the substrate to the top of any of the wires. The bottom surface of the transparent layer has a central region facing the sensor chip and a ring-shaped supporting region surrounded by the central region. The support is arranged outside the sensor chip and abuts against the supporting region.

First claim

What is claimed is:

1 . A sensor package structure, comprising:
a substrate having an upper surface and a lower surface opposing to the upper surface, wherein the substrate includes a plurality of solder pads arranged on the upper surface; a sensor chip having a top surface and a bottom surface opposing to the top surface, wherein the bottom surface of the sensor chip is disposed on the upper surface of the substrate and surrounded by the solder pads, and the sensor chip includes a plurality of connecting pads arranged on the top surface; a plurality of wires, wherein the terminals on one end of the wires are respectively connected to the solder pads, and the terminals on the other end of the wires are respectively connected to the connecting pads; a transparent layer having a first surface and a second surface opposing to the first surface, wherein the second surface has a central region facing the sensor chip and a ring-shaped supporting region enclosing the central region; a support disposed on the upper surface of the substrate and arranged outside the sensor chip, wherein a top side of the support abuts against the supporting region of the transparent layer, a part of each of the wires is embedded in the support, and a height from the upper surface of the substrate to the top of the support is larger than a height from the upper surface of the substrate to the top of any of the wires; and a packaging compound disposed on the upper surface of the substrate and covering a side edge of the support and a side edge of the transparent layer.

2 . The sensor package structure as claimed in claim 1 , wherein the support includes:
a supporting layer; and a combining layer disposed on the supporting layer, wherein a top side of the combining layer abuts against the supporting region of the transparent layer.

3 . The sensor package structure as claimed in claim 2 , wherein a height from the upper surface of the substrate to the top of the supporting layer is smaller than or equal to a height from the upper surface of the substrate to the top surface of the sensor chip, the part of each of the wires is embedded in the combining layer, and the supporting layer does not contact with any of the wires.

4 . The sensor package structure as claimed in claim 3 , wherein the combining layer is arranged between the supporting layer and the supporting region of the transparent layer, and the combining layer does not contact with any of the solder pads.

5 . The sensor package structure as claimed in claim 3 , wherein the combining layer is disposed on the upper surface of the substrate, and the solder pads are embedded in the combining layer.

6 . The sensor package structure as claimed in claim 5 , wherein the combining layer includes:
a first layer, being ring-shaped and disposed on the supporting layer and the upper surface of the substrate, the solder pads being embedded in the first layer, wherein a height from the upper surface of the substrate to the top of the first layer is larger than a height from the upper surface of the substrate to the top surface of the sensor chip; and a second layer being ring-shaped and disposed on the first layer, wherein a top side of the second layer abuts against the supporting region of the transparent layer.

7 . The sensor package structure as claimed in claim 6 , wherein the packaging compound includes:
a molding compound disposed on the upper surface of the substrate and covering a side edge of the first layer; and a liquid compound disposed on the molding compound and covering a side edge of the second layer and the side edge of the transparent layer.

8 . The sensor package structure as claimed in claim 2 , wherein a height from the upper surface of the substrate to the top of the supporting layer is larger than a height form the upper surface of the substrate to the top surface of the sensor chip, and the part of each of the wires is embedded in the supporting layer.

9 . The sensor package structure as claimed in claim 8 , wherein the packaging compound includes:
a molding compound disposed on the upper surface of the substrate and covering a side edge of the supporting layer; and a liquid compound disposed on the molding compound and covering a side edge of the combining layer and the side edge of the transparent layer.

10 . The sensor package structure as claimed in claim 8 , wherein the supporting layer includes an extending portion disposed on the top surface of the sensor chip and arranged outside the connecting pads.

11 . The sensor package structure as claimed in claim 2 , wherein the supporting layer is disposed on the upper surface of the substrate and arranged between the sensor chip and the solder pads.

12 . The sensor package structure as claimed in claim 1 , wherein the top surface of the sensor chip has a sensing region and a ring-shaped wiring region arranged around the sensing region, an area of the sensing region substantially takes 60˜95% of an area of the top surface, and the connecting pads are arranged on the wiring region.

13 . The sensor package structure as claimed in claim 12 , wherein the area of the sensing region substantially takes 80˜90% of the area of the top surface.

14 . The sensor package structure as claimed in claim 1 , wherein the support has a ring shape and covers at least a part of a side edge of the sensor chip.

15 . The sensor package structure as claimed in claim 1 , wherein the support has a ring shape, and the support and a side edge of the sensor chip have a gap therebetween.

16 . The sensor package structure as claimed in claim 1 , wherein the support does not contact with the top surface of the sensor chip.

Assignees

• Kingpak Tech Inc

Inventors

• Chen Jian-Ru
• Yang Jo-Wei
• Hung Li-Chun
• Tu Hsiu-Wen
• Hsin Chung-Hsien

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/124

  the encapsulations having cavities other than that occupied by chips · CPC title

• H10W74/121

  by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title