Memory system and operating method of the same

Patent metadata

Field	Value
Publication number	US-2019056888-A1
Application number	US-201815965450-A
Country	US
Kind code	A1
Filing date	Apr 27, 2018
Priority date	Aug 17, 2017
Publication date	Feb 21, 2019
Grant date	—

Abstract

Disclosed is a memory system includes a memory device including a plurality of memory blocks, a write operation management circuit configured to update write operation counts for the plurality of memory blocks, a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks, a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block, and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

First claim

What is claimed is:

1 . A memory system comprising:
a memory device including a plurality of memory blocks; a write operation management circuit configured to update write operation counts for the plurality of memory blocks; a first block detector configured to detect a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which a write operation has been performed among the plurality of memory blocks; a second detector configured to detect a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block; and a controller configured to copy, if the hot memory block and the cold memory block are detected by the first and second detectors, data of the detected hot memory block or data of the detected cold memory block.

2 . The memory system of claim 1 , wherein, when the write operation management circuit updates the write operation counts for the plurality of memory blocks, the first detector detects the first memory block as the hot memory block if the first operation count value is greater than an average write operation count of the plurality of memory blocks by a first reference value or more.

3 . The memory system of claim 2 , wherein, when the first detector detects the first memory block as the hot memory block, the second detector detects, as the cold memory block, a memory block, of which the second operation count value is less than the average write operation count of the plurality of memory blocks by the first reference value or more, among the second memory blocks.

4 . The memory system of claim 1 , wherein the write operation management circuit comprises:
a counter configured to count the write operation counts for the plurality of memory blocks; and a mapping table configured to store a relationship between addresses of the plurality of memory blocks and the counted write operation counts.

5 . The memory system of claim 4 , wherein the write operation management circuit sums the counted write operation counts for the plurality of memory blocks and stores a value obtained by dividing the sum of the write operation counts by the number of the memory blocks, to the mapping table as an average write operation count of the plurality of memory blocks.

6 . The memory system of claim 1 , wherein the memory device includes a plurality of memory regions each of which is formed by grouping the plurality of memory blocks.

7 . The memory system of claim 6 , wherein the write operation management circuit classifies each of the plurality of memory regions as a hot memory region or a cold memory region depending on whether or not a total write operation count of the corresponding memory region is a second reference value or more.

8 . The memory system of claim 7 ,
wherein, when the hot memory block and the cold memory block are detected from a hot memory region, the controller copies the data of the detected cold memory block to a free memory block of the cold memory region, and wherein, when the hot memory block and the cold memory block are detected from a cold memory region, the controller copies the data of the detected hot memory block to a free memory block of the hot memory region.

9 . The memory system of claim 7 , wherein the write operation management circuit comprises:
a counter configured to count the write operation counts for the plurality of memory blocks; and a mapping table configured to store a relationship between addresses of the plurality of memory blocks and the counted write operation counts.

10 . The memory system of claim 9 , wherein the write operation management circuit stores a value obtained by summing the counted write operation counts for the memory blocks included in each of the memory regions, to the mapping table as the total write operation count of the corresponding memory region.

11 . An operating method for a memory system comprising:
updating write operation counts for a plurality of memory blocks according to a write operation; detecting a hot memory block based on a first operation count value corresponding to the write operation count of a first memory block on which the write operation has been performed among the plurality of memory blocks; detecting a cold memory block based on a second operation count value corresponding to the write operation count of each of second memory blocks adjacent to the first memory block; and copying, if the hot memory block and the cold memory block are detected, data of the detected hot memory block or data of the detected cold memory block.

12 . The operating method of claim 11 , wherein the detecting of the hot memory block comprises:
checking the first operation count value when the write operation counts for the plurality of memory blocks are updated; comparing the checked first operation count value with an average write operation count of the plurality of memory blocks; and detecting the first memory block as the hot memory block when the checked first operation count value is greater than the average write operation count by a first reference value or more as a result of the comparing.

13 . The operating method of claim 12 , wherein the detecting of the cold memory block comprises:
checking the second operation count value when the first memory block is detected as the hot memory block; comparing the checked second operation count value with the average write operation count of the plurality of memory blocks; and detecting, as the cold memory block, a memory block, of which the checked second operation count value is less than the average write operation count of the plurality of memory blocks by the first reference value or more, among the second memory blocks.

14 . The operating method of claim 11 , wherein the updating of the write operation counts for the plurality of memory blocks comprises:
counting the write operation counts for the plurality of memory blocks; summing the counted write operation counts for the plurality of memory blocks; and obtaining an average write operation count of the plurality of memory blocks by dividing the sum of the write operation counts by the number of the memory blocks.

15 . The operating method of claim 11 , wherein the memory system includes a plurality of memory regions each of which is formed by grouping the plurality of memory blocks.

16 . The operating method of claim 15 , further comprising:
comparing a total write operation count of each of the plurality of memory regions with a second reference value; classifying, as a hot memory region, a memory region having a total write operation count is the second reference value or more among the plurality of memory regions as a result of the comparing; and classifying, as a cold memory region, a memory region having a total write operation count is less than the second reference value among the plurality of memory regions as a result of the comparing.

17 . The operating method of claim 16 , wherein the copying of the data of the detected hot memory block or the data of the detected cold memory block comprises:
copying, when the hot memory block and the cold memory block are detected from a hot memory region, the data of the detected cold memory block to a free memory block of the cold memory region; and copying, when the hot memory block and the cold memory block are detected from a cold memory region, the data of the detected hot memory block to a free memory block

Assignees

• Sk Hynix Inc

Inventors

• Kwon Jung-Hyun
• JO Sang-Gu
• Park Jong-Hyun

Classifications

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F2212/7211

  Wear leveling · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F3/064

  Management of blocks · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title