Adaptive granularity write tracking

Patent metadata

Field	Value
Publication number	US-2019034340-A1
Application number	US-201715855104-A
Country	US
Kind code	A1
Filing date	Dec 27, 2017
Priority date	Dec 27, 2017
Publication date	Jan 31, 2019
Grant date	—

Abstract

An embodiment of a semiconductor package apparatus may include technology to create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory, identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and set a flag in the tracking structure to indicate that the memory location had the identified write request. Other embodiments are disclosed and claimed.

First claim

We claim:

1 . An electronic processing system, comprising:
a processor; persistent memory communicatively coupled to the processor; a memory controller communicatively coupled to the processor and the persistent memory; and logic communicatively coupled to the memory controller to:
create a tracking structure for the memory controller to track a range of memory addresses of the persistent memory,
identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and
set a flag in the tracking structure to indicate that the memory location had the identified write request.

2 . The system of claim 1 , wherein the logic is further to:
create the tracking structure based on provided memory address information.

3 . The system of claim 1 , wherein the logic is further to:
create the tracking structure with a bitmap structure; and set a bit in the bitmap structure to indicate that the memory location had the identified write request.

4 . The system of claim 3 , wherein the logic is further to:
create the bitmap structure with a hierarchical bitmap structure.

5 . The system of claim 1 , wherein the logic is further to:
determine if one or more memory locations corresponding to data moved from the persistent memory to another storage region is within the range of tracked memory locations; and clear one or more flags in the tracking structure corresponding to one or more memory locations of the moved data determined to be within the range of tracked memory locations.

6 . The system of claim 1 , wherein the flag corresponds to a unit of memory having a memory size of a 2 N times multiple of a cacheline size, where N is greater than or equal to zero.

7 . A semiconductor package apparatus, comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable logic and fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory,
identify a write request at the memory controller for a memory location within the range of tracked memory addresses, and
set a flag in the tracking structure to indicate that the memory location had the identified write request.

8 . The apparatus of claim 7 , wherein the logic is further to:
create the tracking structure based on provided memory address information.

9 . The apparatus of claim 7 , wherein the logic is further to:
create the tracking structure with a bitmap structure; and set a bit in the bitmap structure to indicate that the memory location had the identified write request.

10 . The apparatus of claim 9 , wherein the logic is further to:
create the bitmap structure with a hierarchical bitmap structure.

11 . The apparatus of claim 7 , wherein the logic is further to:
determine if one or more memory locations corresponding to data moved from the persistent memory to another storage region is within the range of tracked memory locations; and clear one or more flags in the tracking structure corresponding to one or more memory locations of the moved data determined to be within the range of tracked memory locations.

12 . The apparatus of claim 7 , wherein the flag corresponds to a unit of memory having a memory size of a 2 N times multiple of a cacheline size, where N is greater than or equal to zero.

13 . A method of controlling memory, comprising:
creating a tracking structure for a memory controller to track a range of memory addresses of a persistent memory; identifying a write request at the memory controller for a memory location within the range of tracked memory addresses; and setting a flag in the tracking structure to indicate that the memory location had the identified write request.

14 . The method of claim 13 , wherein the logic is further to:
creating the tracking structure based on provided memory address information.

15 . The method of claim 13 , wherein the logic is further to:
creating the tracking structure with a bitmap structure; and setting a bit in the bitmap structure to indicate that the memory location had the identified write request.

16 . The method of claim 15 , wherein the logic is further to:
creating the bitmap structure with a hierarchical bitmap structure.

17 . The method of claim 13 , wherein the logic is further to:
determining if one or more memory locations corresponding to data moved from the persistent memory to another storage region is within the range of tracked memory locations; and clearing one or more flags in the tracking structure corresponding to one or more memory locations of the moved data determined to be within the range of tracked memory locations.

18 . The method of claim 13 , wherein the flag corresponds to a unit of memory having a memory size of a 2 N times multiple of a cacheline size, where N is greater than or equal to zero.

19 . At least one computer readable medium, comprising a set of instructions, which when executed by a computing device, cause the computing device to:
create a tracking structure for a memory controller to track a range of memory addresses of a persistent memory; identify a write request at the memory controller for a memory location within the range of tracked memory addresses; and set a flag in the tracking structure to indicate that the memory location had the identified write request.

20 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
create the tracking structure based on provided memory address information.

21 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
create the tracking structure with a bitmap structure; and set a bit in the bitmap structure to indicate that the memory location had the identified write request.

22 . The at least one computer readable medium of claim 21 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
create the bitmap structure with a hierarchical bitmap structure.

23 . The at least one computer readable medium of claim 19 , comprising a further set of instructions, which when executed by the computing device, cause the computing device to:
determine if one or more memory locations corresponding to data moved from the persistent memory to another storage region is within the range of tracked memory locations; and clear one or more flags in the tracking structure corresponding to one or more memory locations of the moved data determined to be within the range of tracked memory locations.

24 . The at least one computer readable medium of claim 19 , wherein the flag corresponds to a unit of memory having a memory size of a 2 N times multiple of a cacheline size, where N is greater than or equal to zero.

Assignees

• Intel Corp

Inventors

• Doshi Kshitij A
• Guim Bernat Francesc
• Rivas Barragan Daniel
• Prabhakaran Suraj

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F12/0238 Primary

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0831 Primary

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title