Frequency/phase synthesizer noise cancellation

US2019028209A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019028209-A1
Application numberUS-201815893461-A
CountryUS
Kind codeA1
Filing dateFeb 9, 2018
Priority dateJul 20, 2017
Publication dateJan 24, 2019
Grant date

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

An open-loop feed-forward cross-correlator noise cancellation device includes a synthesizer to generate a synthesized output clock signal based on a reference clock signal. The open-loop feed-forward cross-correlator noise cancellation device also includes a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal. The open-loop feed-forward cross-correlator noise cancellation device further includes a signal control delay line coupled to the cross-correlator device to generate an anti-phase noise signal based on the cross-correlated output signal to counter uncorrelated phase noise from additional circuitry of the synthesizer.

First claim

Opening claim text (preview).

What is claimed is: 1 . An open-loop feed-forward cross-correlator noise cancellation device, comprising: a synthesizer to generate a synthesized output clock signal based at least in part on a reference clock signal; a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal; and a delay line coupled to the cross-correlator device, a delay of the delay line based at least in part on the cross-correlated output signal. 2 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the delay line is configured to generate an anti-phase noise signal based at least in part on the cross-correlated output signal to counter uncorrelated phase noise from additional circuitry of the synthesizer. 3 . The open-loop feed-forward cross-correlator noise cancellation device of claim 2 , further comprising a combiner to combine the cross-correlated output signal with a reference signal, in which the anti-phase noise signal is based at least in part on the reference signal and the cross-correlated output signal. 4 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , further comprising an open-loop filter coupled between the cross-correlator device and the delay line. 5 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the delay line comprises a voltage controlled delay line, a current controlled delay line or a charge controlled delay line. 6 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the delay line comprises a low dropout (LDO) regulator and a buffer. 7 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the cross-correlator device comprises a phase detector. 8 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the synthesizer comprises a phase locked loop, a delay locked loop, or a phase/frequency synthesizer. 9 . The open-loop feed-forward cross-correlator noise cancellation device of claim 1 , in which the open-loop feed-forward cross-correlator noise cancellation device is incorporated in a reference clock signal and synthesizer system for an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a central processing unit (CPU), a receive block of a wireless communication device or a transmit block of the wireless communication device. 10 . A method to achieve open-loop feed-forward cross-correlator noise cancellation, comprising: generating a synthesized output clock signal based at least in part on a reference clock signal; cross-correlating the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal; and generating an anti-phase noise signal based at least in part on the cross-correlated output signal to counter uncorrelated phase noise from circuitry of a synthesizer. 11 . The method to achieve open-loop feed-forward cross-correlator noise cancellation of claim 10 , further comprising filtering out correlated input noise from the reference clock signal leaving the uncorrelated phase noise. 12 . The method to achieve open-loop feed-forward cross-correlator noise cancellation of claim 10 , further comprising combining the cross-correlated output signal with a reference signal, in which the anti-phase noise signal is based at least in part on the reference signal and the cross-correlated output signal. 13 . The method to achieve open-loop feed-forward cross-correlator noise cancellation of claim 10 , in which the method is implemented using an open-loop feed-forward cross-correlator noise cancellation device. 14 . The method to achieve open-loop feed-forward cross-correlator noise cancellation of claim 13 , further comprising incorporating the open-loop feed-forward cross-correlator noise cancellation device in a reference clock signal and synthesizer system for an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a central processing unit (CPU), a receive block of a wireless communication device or a transmit block of the wireless communication device. 15 . An open-loop feed-forward cross-correlator noise cancellation device, comprising: means for generating a synthesized output clock signal based at least in part on a reference clock signal; a cross-correlator device, coupled to the synthesized output clock signal generating means, to receive the reference clock signal and the synthesized output clock signal and to cross-correlate the reference clock signal and the synthesized output clock signal to generate a cross-correlated output signal; and means for generating a delay based at least in part on the cross-correlated output signal, the delay generating means coupled to the cross-correlator device. 16 . The open-loop feed-forward cross-correlator noise cancellation device of claim 15 , in which the delay generating means is configured to generate an anti-phase noise signal based at least in part on the cross-correlated output signal to counter uncorrelated phase noise from additional circuitry of the synthesized output clock signal generating means. 17 . The open-loop feed-forward cross-correlator noise cancellation device of claim 16 , further comprising a combiner to combine the cross-correlated output signal with a reference signal, in which the anti-phase noise signal is based at least in part on the reference signal and the cross-correlated output signal. 18 . The open-loop feed-forward cross-correlator noise cancellation device of claim 15 , further comprising an open-loop filter coupled between the cross-correlator device and the delay generating means. 19 . The open-loop feed-forward cross-correlator noise cancellation device of claim 15 , in which the cross-correlator device comprises a phase detector. 20 . The open-loop feed-forward cross-correlator noise cancellation device of claim 15 , in which the open-loop feed-forward cross-correlator noise cancellation device is incorporated in a reference clock signal and synthesizer system for an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a central processing unit (CPU), a receive block of a wireless communication device or a transmit block of the wireless communication device.

Assignees

Inventors

Classifications

  • by comparing receiver clock with transmitter clock · CPC title

  • H04B15/00Primary

    Suppression or limitation of noise or interference (by means associated with receiver H04B1/10) · CPC title

  • H03L1/00Primary

    Stabilisation of generator output against variations of physical values, e.g. power supply · CPC title

  • Compensating for non-linear characteristics of the controlled oscillator · CPC title

  • by local oscillators of receivers · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US2019028209A1 cover?
An open-loop feed-forward cross-correlator noise cancellation device includes a synthesizer to generate a synthesized output clock signal based on a reference clock signal. The open-loop feed-forward cross-correlator noise cancellation device also includes a cross-correlator device coupled to the synthesizer to receive the reference clock signal and the synthesized output clock signal and to cr…
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H04B15/00. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).