Mixer s11 control via sum component termination

US2019028124A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2019028124-A1
Application numberUS-201816040460-A
CountryUS
Kind codeA1
Filing dateJul 19, 2018
Priority dateJul 20, 2017
Publication dateJan 24, 2019
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.

First claim

Opening claim text (preview).

What is claimed is: 1 . A mixer termination circuit for a downconverter mixer, comprising: a diplexer circuit coupled to an output of the downconverter mixer, the diplexer circuit configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer. 2 . The mixer termination circuit of claim 1 , in which the diplexer circuit comprises a termination resistor. 3 . The mixer termination circuit of claim 2 , further comprising an inductor and a capacitor coupled in series with the termination resistor. 4 . The mixer termination circuit of claim 2 , further comprising an inductor and a capacitor coupled in parallel with the termination resistor. 5 . The mixer termination circuit of claim 1 , in which the diplexer circuit comprises a feedback voltage amplifier. 6 . The mixer termination circuit of claim 1 , in which the diplexer circuit comprises a T-network having a series resistor inductor capacitor (RLC) circuit branch including a termination resistor. 7 . The mixer termination circuit of claim 6 , in which the RLC circuit branch is tuned to a frequency of the sum component. 8 . The mixer termination circuit of claim 1 , in which the diplexer circuit comprises a pi-network having an inductor and a capacitor in parallel with a termination resistor, configured to terminate a sum component output of the downconverter mixer at a resonance frequency of the inductor and the capacitor. 9 . The mixer termination circuit of claim 8 , in which the inductor, the capacitor, and the termination resistor are tuned to a frequency of the sum component present in the output signal of the downconverter mixer. 10 . The mixer termination circuit of claim 1 , in which the diplexer circuit comprises an RC filter, including a load resistor RL in parallel with a shunt capacitor, configured to terminate a difference component output of the downconverter mixer at a baseband frequency. 11 . The mixer termination circuit of claim 1 , in which the sum component present in the output signal has a frequency that is a sum of a frequency of a local oscillator (LO) signal of the downconverter mixer and a frequency of a radio frequency (RF) input signal provided to the downconverter mixer. 12 . The mixer termination circuit of claim 1 , in which the difference component present in the output signal has a frequency that is a difference of a frequency of a radio frequency (RF) input signal provided to the downconverter mixer and a frequency of a local oscillator (LO) signal of the downconverter mixer. 13 . The mixer termination circuit of claim 1 , in which the downconverter mixer comprises a mixer-first downconverter, in which a mixer and an amplifier are in a receive chain and an output of the mixer is fed to the amplifier. 14 . The mixer termination circuit of claim 1 , in which the downconverter mixer comprises a current mode mixer or a voltage mode mixer. 15 . The mixer termination circuit of claim 1 , integrated into a mobile RF receiver. 16 . The mixer termination circuit of claim 15 , in which the mobile RF receiver is integrated into an RF integrated circuit (RFIC) system. 17 . A method of controlling an input impedance of a downconverter mixer, comprising: receiving an output signal from the downconverter mixer at a mixer termination circuit; attenuating a sum component of the output signal using a first branch of the mixer termination circuit; and passing a difference component of the output signal to an output of the mixer termination circuit. 18 . The method of claim 17 , in which the sum component has a frequency that is a sum of a frequency of a local oscillator (LO) signal of the downconverter mixer and a frequency of a radio frequency (RF) input signal provided to the downconverter mixer. 19 . The method of claim 17 , in which the difference component has a frequency that is a difference of a frequency of a radio frequency (RF) input signal provided to the downconverter mixer and a frequency of a local oscillator (LO) signal of the downconverter mixer. 20 . The method of claim 17 , in which attenuating the sum component comprises attenuating using a termination resistor at a sum component output of the downconverter mixer at a resonance frequency. 21 . The method of claim 17 , in which passing the difference component comprises passing the difference component to a difference component output of the downconverter mixer. 22 . The method of claim 17 , in which attenuating the sum component comprises attenuating using a high frequency path through a series resistor inductor capacitor (RLC) branch of a diplexer filter circuit including a termination resistor at a resonance frequency of an inductor and a capacitor of the series RLC branch. 23 . A mixer termination circuit for a downconverter mixer, the mixer termination circuit comprising: means for attenuating a sum component present in an output signal of the downconverter mixer; and means for passing a difference component present in the output signal of the downconverter mixer. 24 . The mixer termination circuit of claim 23 , in which the downconverter mixer comprises a mixer-first downconverter, in which a mixer and an amplifier are in a receive chain and an output of the mixer is coupled to an input of the amplifier. 25 . The mixer termination circuit of claim 23 , in which the downconverter mixer comprises a current mode mixer or a voltage mode mixer. 26 . The mixer termination circuit of claim 23 , integrated into a mobile RF receiver. 27 . The mixer termination circuit of claim 26 , in which the mobile RF receiver is integrated into an RF integrated circuit system. 28 . The mixer termination circuit of claim 23 , in which the sum component present in the output signal has a frequency that is a sum of a frequency of a local oscillator (LO) signal of the downconverter mixer and a frequency of a radio frequency (RF) input signal provided to the downconverter mixer. 29 . The mixer termination circuit of claim 23 , in which the difference component present in the output signal has a frequency that is a difference of a frequency of a radio frequency (RF) input signal provided to the downconverter mixer and a frequency of a local oscillator (LO) signal of the downconverter mixer.

Assignees

Inventors

Classifications

  • Circuits · CPC title

  • H04B1/006Primary

    using switches for selecting the desired band (H04B1/0057 takes precedence) · CPC title

  • H04B1/18Primary

    Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

  • wherein the AD/DA conversion occurs at baseband stage · CPC title

  • Neutralising, balancing, or compensation arrangements · CPC title

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What does patent US2019028124A1 cover?
A mixer termination circuit for a downconverter mixer includes a diplexer circuit coupled to an output of the downconverter mixer. The diplexer circuit is configured to separately terminate a sum component present in an output signal of the downconverter mixer and a difference component present in the output signal of the downconverter mixer.
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H04B1/006. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Jan 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).