Semiconductor device
US-2024421022-A1 · Dec 19, 2024 · US
Method of manufacturing semiconductor device
US2019027381A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2019027381-A1 |
| Application number | US-201816037694-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jul 17, 2018 |
| Priority date | Jul 19, 2017 |
| Publication date | Jan 24, 2019 |
| Grant date | — |
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- Title
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- Abstract
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- First independent claim
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Abstract
Official abstract text for this publication.
A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold, wherein one metal plate is in contact with a bottom surface of the cavity and a space is provided above the other metal plate; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method of manufacturing a semiconductor device that comprises a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, each of the pair of metal plates being exposed at corresponding one of both surfaces of the resin package, the method comprising: preparing an assembly in which the semiconductor element is connected to the pair of metal plates; setting the assembly in a cavity of a mold configured to form the resin package, wherein one metal plate of the pair of metal plates is in contact with a bottom surface of the cavity and a space is provided above the other metal plate of the pair of metal plates; forming the resin package by injecting a molten resin into the cavity so as to cover an upper side of the other metal plate, stopping the injecting of the molten resin with a part of the space on an upper side of the cavity unfilled, and hardening the molten resin injected into the cavity; and removing a resin covering the other metal plate. 2 . The method as in claim 1 , wherein a recess is provided in an area of an upper surface of the cavity, the area facing the other metal plate, and the forming of the resin package comprises stopping the injecting of the molten resin with a part of an inner space of the recess unfilled. 3 . The method as in claim 1 , wherein the assembly comprises two pairs of metal plates, each of the two pairs of metal plates interposing a semiconductor element therebetween, a first joint extends from an edge of a lower metal plate of one pair of the two pairs of metal plates, a second joint extends from an edge of an upper metal plate of the other pair of the two pairs of metal plates, the first joint and the second joint overlap each other in a normal direction of the metal plates, and the first joint and the second joint are connected to each other via a solder, and in the cavity, the second joint is in contact with an upper surface of the cavity.
Assignees
Inventors
Classifications
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title
Encapsulations, e.g. protective coatings · CPC title
changes in dispositions · CPC title
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Frequently asked questions
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- What does patent US2019027381A1 cover?
- A method of manufacturing a semiconductor device that includes a resin package sealing a semiconductor element and a pair of metal plates interposing the semiconductor element therebetween, in which each of the pair of metal plates is exposed at corresponding one of both surfaces of the resin package is disclosed. The method may include preparing an assembly in which the semiconductor element i…
- Who is the assignee on this patent?
- Toyota Motor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W40/778. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Jan 24 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).