Goa signal determining circuit, determining method, gate driver circuit and display device

Patent metadata

Field	Value
Publication number	US-2019027079-A1
Application number	US-201715577402-A
Country	US
Kind code	A1
Filing date	May 3, 2017
Priority date	Jun 23, 2016
Publication date	Jan 24, 2019
Grant date	—

Abstract

A GOA signal determining circuit and method thereof, gate driver circuit, and display device are provided. The GOA signal determining circuit is connected to an input end of a GOA unit, at least two clock signal ends of the GOA unit, and a control end of a reset unit of a PU node in the GOA unit. The GOA signal determining circuit detects a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end and the signal of the at least two clock signal ends are abnormal.

First claim

1 . A GOA signal determining circuit,
connecting an input end of a GOA unit, at least two clock signal ends of the GOA unit and a control end of a reset unit of a PU node in the GOA unit; wherein the GOA signal determining circuit is configured to detect a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and wherein upon determining both of the signal of the input end of the GOA unit and the signal of the at least two clock signal ends of the GOA unit involving an anomaly, the GOA signal determining circuit outputs a control signal to the reset unit of the PU node to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, wherein, the at least two clock signal ends comprises at least one pair of clock signal ends having input signals complemented with each other, the PU node of the GOA unit is connected to a gate of the output transistor of the GOA unit, and a drain of the output transistor is connected to an output end of the GOA unit, and is configured to output a driving signal to a gate line connected to the output end of the GOA unit.

2 . The GOA signal determining circuit according to claim 1 further comprising a NOR gate, wherein
the input end of the GOA unit and the at least two clock signal ends of the GOA unit are respectively connected to one of input ends of the NOR gate, and
an output end of the NOR gate is connected to the control end of the reset unit.

3 . The GOA signal determining circuit according to claim 2 , wherein the output end of the NOR gate is connected to the control end of the reset unit through a signal amplifier.

4 . The GOA signal determining circuit according to claim 1 , wherein
the GOA signal determining circuit is further connected to a first level end and a second level end, the GOA signal determining circuit further comprises a pull-up unit and at least two pull-down units; wherein the pull-up unit is connected to the first level end and the control end of the reset unit, and is configured to output a signal of the first level end to the control end of the reset unit under a control of the signal of the first level end; each of the pull-down units is connected to the input end of the GOA unit or one of the at least two clock signal ends of the GOA unit; the pull-down unit is further connected to the second level end and the control end of the reset unit; the pull-down unit is configured to output a signal of the second level end to the control end of the reset unit under a control of the signal of the second level end, or to output the signal of the second level end to the control end of the reset unit under a control of the signal of the clock signal end.

5 . The GOA signal determining circuit according to claim 4 , wherein
the pull-up unit comprises a first transistor; a gate and a source of the first transistor are connected to the first level end; and a drain of the first transistor is connected to the control end of the reset unit, and the pull-down unit comprises a second transistor; a gate of the second transistor is connected to the input end of the GOA unit or the clock signal end of the GOA unit; a source of the second transistor is connected to the drain of the first transistor; and a drain of the second transistor is connected to the second level end.

6 . The GOA signal determining circuit according to claim 1 , wherein
the GOA signal determining circuit is further connected to a first level end, a second level end, and a third level end; the GOA signal determining circuit further comprises a first pull-up unit, a second pull-up unit, and at least two pull-down units; wherein, the first pull-up unit is connected to the first level end and the control end of the reset unit, and is configured to output a signal of the first level end to the control end of the reset unit under a control of the signal of the first level end during a first stage; and the second pull-up unit is connected to the third level end and the control end of the reset unit, and is configured to output a signal of the third level end to the control end of the reset unit under a control of the signal of the third level end during a second stage, and each of the pull-down units is connected to the input end of the GOA unit or one of the at least two clock signal ends of the GOA unit; the pull-down unit is further connected to the second level end and the control end of the reset unit; the pull-down unit is configured to output a signal of the second level end to the control end of the reset unit under a control of the signal of the input end of the GOA unit, or output the signal of the second level end to the control end of the reset unit under a control of the signal of the clock signal end.

7 . The GOA signal determining circuit according to claim 6 , wherein
the first pull-up unit comprises a first transistor; a gate and a source of the first transistor are connected to the first level end; and a drain of the first transistor is connected to the control end of the reset unit, the second pull-up unit comprises a third transistor; a gate and a source of the third transistor are connected to the third level end; and a drain of the third transistor is connected to the drain of the first transistor, and the pull-down unit comprises a second transistor; a gate of the second transistor is connected to the input end of the GOA unit or the clock signal end of the GOA unit; a source of the second transistor is connected to the drain of the first transistor; and a drain of the second transistor is connected to the second level end.

8 . The GOA signal determining circuit according to claim 4 further comprises a capacitor, wherein a first electrode of the capacitor is connected to the control end of the reset unit, and a second electrode of the capacitor is connected to the second level end.

9 . A gate driver circuit, comprising:
a plurality of GOA units connected in series and the GOA signal determining circuit according to claim 1 .

10 . A display device, comprising the gate driver circuit according to claim 9 .

11 . A method of determining a GOA signal, comprising:
connecting a GOA signal determining circuit with an input end of a GOA unit, at least two clock signal ends of the GOA unit and a control end of a reset unit of a PU node in the GOA unit; detecting a signal of the input end of the GOA unit and a signal of the at least two clock signal ends of the GOA unit, and outputting the control signal to the reset unit of the PU node in the GOA unit so as to control the reset unit to output a reset signal to the PU node to turn off an output transistor of the GOA unit, upon determining both of the signal of the input end of the GOA unit and the signal of the at least two clock signal ends of the GOA unit involving an anomaly, the at least two clock signal ends comprising at least one pair of clock signal ends having input signals complemented with each other; the PU node of the GOA unit being connected to a gate of the output transistor; a drain of the output transistor being connected to an output end of the GOA unit, and being configured to output a driving signal to a gate line connected to the output end of the GOA unit.

12 . (canceled)

13 . (canceled)

14 . (canceled)

15 . (canceled)

16 . (canceled)

17 . (canceled)

18 . The GOA signal determining circuit according to claim 5 further comprises a capacitor,
wherein a first electrode of the capacitor is connected to the control end of the res

Assignees

• Boe Technology Group Co Ltd

Inventors

• Shang Guangliang
• Yao Xing
• Han Mingfu
• Han Seung-Woo
• Im Yun-Sik
• Lv Jing
• Huang Yinglong
• Jun Jung-Mok
• Dong Xue
• Zheng Haoliang
• Yuan Lijun
• Wang Zhichong
• Kim Ji Ha

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title