Predictive caching for check word snooping in high performance ficon

Patent metadata

Field	Value
Publication number	US-2019026180-A1
Application number	US-201816047585-A
Country	US
Kind code	A1
Filing date	Jul 27, 2018
Priority date	Sep 26, 2016
Publication date	Jan 24, 2019
Grant date	—

Abstract

Technical solutions are described for computing data check word for a host request for an I/O processing operation at a host computer system that communicates with a control unit. An example method includes obtaining information for a first I/O operation at a channel subsystem in the host computer system, and accessing an address control word (ACW) of the first I/O operation. The ACW is stored in the local channel memory, and the ACW includes a first data check seed-value. The method also includes computing a first data check word based on the first data check seed-value from the ACW. The method also includes obtaining information for a second I/O operation at the channel subsystem, and in response to the second i/o operation corresponding to said ACW of the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

First claim

What is claimed is:

1 . A computer implemented method for computing data check word for a host request for performing an input/output (I/O) processing operation at a host computer system configured for communication with a control unit, the method comprising:
obtaining information relating to a first I/O operation at a channel subsystem in the host computer system, the channel subsystem including at least one channel having a channel processor and a local channel memory; accessing an address control word (ACW) corresponding to the first I/O operation, the ACW specifying one or more host memory locations for transfer of data between the host computer system and the control unit, the ACW being stored in the local channel memory, the ACW including a first data check seed-value; computing a first data check word based on the first data check seed-value from the ACW; obtaining information relating to a second I/O operation at the channel subsystem; and in response to the second I/O operation corresponding to said ACW that is corresponding to the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

2 . The computer implemented method of claim 1 , wherein, in response to the second I/O operation not corresponding to the ACW of the first I/O operation, computing the second data check word based on the second data check seed-value from a second ACW corresponding to the second I/O operation.

3 . The computer implemented method of claim 1 , further comprising: storing the first data check word as the second data check seed-value in the cache memory.

4 . The computer implemented method of claim 3 , further comprising: in response to the second I/O operation not corresponding to the ACW of the first I/O operation, storing the second data check seed-value from the cache memory in said ACW.

5 . The computer implemented method of claim 3 , further comprising: in response to entering an idle state, storing the second data check seed-value from the cache memory in said ACW.

6 . The computer implemented method of claim 5 , wherein the idle state is entered in response to a predetermined duration being elapsed without another I/O operation since completing the second I/O operation.

7 . The computer implemented method of claim 1 , wherein the data check word is one from a group consisting of a cyclical redundancy check (CRC) word, a longitudinal redundancy check (LRC) word, and a checksum word.

8 . The computer implemented method of claim 1 , wherein the cache memory has a lower latency than the local channel memory.

9 . The computer implemented method of claim 1 , wherein the first I/O operation and the second I/O operation are part of a common host request.

10 . A system for computing data check word for a host request for performing an input/output (I/O) processing operation at a host computer system configured for communication with a control unit, the system comprising:
a memory; a cache memory that has lower latency than the memory; a timer; and a data router hardware coupled to the memory, the cache memory, and the timer, and the data router configured to perform a method comprising:
obtaining information relating to a first I/O operation at a channel subsystem in the host computer system, the channel subsystem including at least one channel having a channel processor and a local channel memory;
accessing an address control word (ACW) corresponding to the first I/O operation, the ACW specifying one or more host memory locations for transfer of data between the host computer system and the control unit, the ACW being stored in the local channel memory, the ACW including a first data check seed-value;
computing a first data check word based on the first data check seed-value from the ACW;
obtaining information relating to a second I/O operation at the channel subsystem; and
in response to the second I/O operation corresponding to said ACW that is corresponding to the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

11 . The system of claim 10 , wherein, in response to the second I/O operation not corresponding to the ACW of the first I/O operation, computing the second data check word based on the second data check seed-value from a second ACW corresponding to the second I/O operation.

12 . The system of claim 10 , wherein the method further comprises storing the first data check word as the second data check seed-value in the cache memory.

13 . The system of claim 12 , wherein the method further comprises: in response to the second I/O operation not corresponding to the ACW of the first I/O operation, storing the second data check seed-value from the cache memory in said ACW.

14 . The system of claim 12 , wherein the method further comprises: in response to entering an idle state, storing the second data check seed-value from the cache memory in said ACW.

15 . The system of claim 14 , wherein the idle state is entered in response to a predetermined duration being elapsed without another I/O operation since completing the second I/O operation.

16 . The system of claim 10 , wherein the data check word is one from a group consisting of a cyclical redundancy check (CRC) word, a longitudinal redundancy check (LRC) word, and a checksum word.

17 . A computer program product for a host request for performing an input/output (I/O) processing operation at a host computer system configured for communication with a control unit, the computer program product comprising a computer readable storage medium, the computer readable storage medium comprising computer executable instructions, wherein the computer readable storage medium comprises instructions to perform a method comprising:
obtaining information relating to a first I/O operation at a channel subsystem in the host computer system, the channel subsystem including at least one channel having a channel processor and a local channel memory; accessing an address control word (ACW) corresponding to the first I/O operation, the ACW specifying one or more host memory locations for transfer of data between the host computer system and the control unit, the ACW being stored in the local channel memory, the ACW including a first data check seed-value; computing a first data check word based on the first data check seed-value from the ACW; obtaining information relating to a second I/O operation at the channel subsystem; and in response to the second I/O operation corresponding to said ACW that is corresponding to the first I/O operation, computing a second data check word based on a second data check seed-value from a cache memory.

18 . The computer program product of claim 17 , wherein, in response to the second I/O operation not corresponding to the ACW of the first I/O operation, computing the second data check word based on the second data check seed-value from a second ACW corresponding to the second I/O operation.

19 . The computer program product of claim 17 , wherein the method further comprises: storing the first data check word as the second data check seed-value in the cache memory.

20 . The computer program product of claim 18 , wherein the method further comprises: in response to the second I/O operation not corresponding to the ACW of the first I/O operation, storing the second data check seed-value from the cache memory in said ACW.

Assignees

• IBM

Inventors

• Wong Raymond
• Zheng Jie

Classifications

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F12/0862

  with prefetch · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F11/1064 Primary

  in cache or content addressable memories · CPC title