Scan driving circuit and display device

Patent metadata

Field	Value
Publication number	US-2019019461-A1
Application number	US-201715557448-A
Country	US
Kind code	A1
Filing date	Aug 22, 2017
Priority date	Jul 11, 2017
Publication date	Jan 17, 2019
Grant date	—

Abstract

Provided are a scan driving circuit and a display device. Each driving unit comprises a first signal input end receiving a trigger signal or a former stage scan signal, a second signal input end receiving a latter stage scan signal, a first signal output end and a second signal output end connected to a multiplexing circuit; each multiplexing unit comprises a first signal receiving end and a second signal receiving end respectively connected to the first signal output end and the second signal output end, a third signal receiving end receiving the former stage scan signal, a fourth signal receiving end receiving the latter stage scan signal, a fifth signal receiving end receiving a clock signal, a scan signal output end outputting a scan signal for simplifying the circuit and saving the space, which is beneficial for the narrow frame design of the display device.

First claim

What is claimed is:

1 . A scan driving circuit, comprising:
a driving circuit, comprising a plurality of driving units connected in turn, wherein each of the driving units is correspondingly connected to a multiplexing circuit, each of the driving units comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is employed to receive a trigger signal or a former stage scan signal, the second signal input end is employed to receive a latter stage scan signal, the first signal output end and the second signal output end are connected to the multiplexing circuit; and the multiplexing circuit, comprising a plurality of multiplexing units, wherein each of the multiplexing units comprises first to fifth signal receiving ends and a scan signal output end, the first signal receiving end is connected to the first signal output end of the driving unit, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is employed to receive a former stage scan signal, the fourth signal receiving end is employed to receive a latter stage scan signal, the fifth signal receiving end is employed to receive a clock signal, the scan signal output end is employed to output a scan signal to a scan line for driving a pixel unit; wherein each of the driving unit comprises first to fifth controllable switches and a first capacitor, a control end of the first controllable switch is connected to the first signal input end, a first end of the first controllable switch is connected to a voltage end, a second end of the first controllable switch is connected to a control end of the third controllable switch, a first end of the fourth controllable switch, a first end of the fifth controllable switch and the first signal output end, a control end of the second controllable switch is connected to a first end of the second controllable switch and the voltage end, a second end of the second controllable switch is connected to the second signal output end, a first end of the third controllable switch and a control end of the fourth controllable switch, second ends of the third to fifth controllable switches are all grounded, a control end of the fifth controllable switch is connected to the second signal input end, one end of the first capacitor is connected to a first end of the fifth controllable switch, the other end of the first capacitor is grounded; a voltage level of an output signal of the first signal output end of the driving unit is opposite to a voltage level of an output signal of the second signal output end.

2 . A scan driving circuit, comprising:
a driving circuit, comprising a plurality of driving units connected in turn, wherein each of the driving units is correspondingly connected to a multiplexing circuit, each of the driving units comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is employed to receive a trigger signal or a former stage scan signal, the second signal input end is employed to receive a latter stage scan signal, the first signal output end and the second signal output end are connected to the multiplexing circuit; and the multiplexing circuit, comprising a plurality of multiplexing units, wherein each of the multiplexing units comprises first to fifth signal receiving ends and a scan signal output end, the first signal receiving end is connected to the first signal output end of the driving unit, the second signal receiving end is connected to the second signal output end of the driving unit, the third signal receiving end is employed to receive a former stage scan signal, the fourth signal receiving end is employed to receive a latter stage scan signal, the fifth signal receiving end is employed to receive a clock signal, the scan signal output end is employed to output a scan signal to a scan line for driving a pixel unit.

3 . The scan driving circuit according to claim 2 , wherein each of the driving unit comprises first to fifth controllable switches and a first capacitor, a control end of the first controllable switch is connected to the first signal input end, a first end of the first controllable switch is connected to a voltage end, a second end of the first controllable switch is connected to a control end of the third controllable switch, a first end of the fourth controllable switch, a first end of the fifth controllable switch and the first signal output end, a control end of the second controllable switch is connected to a first end of the second controllable switch and the voltage end, a second end of the second controllable switch is connected to the second signal output end, a first end of the third controllable switch and a control end of the fourth controllable switch, second ends of the third to fifth controllable switches are all grounded, a control end of the fifth controllable switch is connected to the second signal input end, one end of the first capacitor is connected to a first end of the fifth controllable switch, the other end of the first capacitor is grounded.

4 . The scan driving circuit according to claim 3 , wherein each of the multiplexing units comprises sixth to tenth controllable switches and a second capacitor, a control end of the sixth controllable switch is connected to the first signal receiving end, a first end of the sixth controllable switch is connected to the voltage end, a second end of the sixth controllable switch is connected to a first end of the seventh controllable switch, a control end of the seventh controllable switch is connected to the third signal receiving end, a second end of the seventh controllable switch is connected to a first end of the eighth controllable switch and a control end of the ninth controllable switch, a control end of the eighth controllable switch is connected to the fourth signal receiving end, a second end of the eighth controllable switch is grounded, a first end of the ninth controllable switch is connected to the fifth signal receiving end, a second end of the ninth controllable switch is connected to a first end of the tenth controllable switch and the scan signal output end, a control end of the tenth controllable switch is connected to the second signal receiving end, a second end of the tenth controllable switch is grounded, one end of the second capacitor is connected to the control end of the ninth controllable switch, the other end of the second capacitor is connected to the second end of the ninth controllable switch.

5 . The scan driving circuit according to claim 4 , wherein the first to tenth controllable switches are all N type thin film transistors, the control ends, the first ends and the second ends of the first to tenth controllable switches respectively are gates, sources and drains of the N type thin film transistors.

6 . The scan driving circuit according to claim 2 , wherein a voltage level of an output signal of the first signal output end of the driving unit is opposite to a voltage level of an output signal of the second signal output end.

7 . A display device, comprising a scan driving circuit, wherein the scan driving circuit comprises:
a driving circuit, comprising a plurality of driving units connected in turn, wherein each of the driving units is correspondingly connected to a multiplexing circuit, each of the driving units comprises a first signal input end, a second signal input end, a first signal output end and a second signal output end, the first signal input end is employed to receive a trigger signal or a former stage scan signal, the second signal input end is employed to receive a latter stage scan signal, the fir

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Shi Longqiang

Classifications

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title

• G09G3/3674

  Details of drivers for scan electrodes · CPC title