Adaptive leading-edge blanking

Patent metadata

Field	Value
Publication number	US-2019013803-A1
Application number	US-201715643766-A
Country	US
Kind code	A1
Filing date	Jul 7, 2017
Priority date	Jul 7, 2017
Publication date	Jan 10, 2019
Grant date	—

Abstract

In some examples, a control circuit is configured to control a transistor, and the control circuit includes a leading-edge detection unit configured to detect a time interval that corresponds to a leading-edge current spike through the transistor, wherein the time interval is independent of temperature. In some examples, the control circuit also includes a blanking unit configured to prevent the control circuit from turning off the transistor during the time interval.

First claim

What is claimed is:

1 . A control circuit configured to control a transistor, the control circuit comprising:
a leading-edge detection unit configured to detect a time interval that corresponds to a leading-edge current spike through the transistor, wherein the time interval is independent of temperature; and a blanking unit configured to prevent the control circuit from turning off the transistor during the time interval.

2 . The control circuit of claim 1 ,
wherein the leading-edge current spike through the transistor comprises:
a rising phase during which an electrical current through the transistor increases; and
a falling phase during which the electrical current through the transistor decreases, and
wherein the leading-edge detection unit is configured to detect the time interval by at least:
starting the time interval when the control circuit turns on the transistor; and
ending the time interval when the electrical current through the transistor increases after the falling phase.

3 . The control circuit of claim 1 , wherein the leading-edge detection unit is configured to detect the time interval of less than or equal to a predetermined time duration.

4 . The control circuit of claim 3 ,
wherein the control circuit is configured to control the transistor by at least turning on the transistor to initiate the leading-edge current spike, wherein the leading-edge detection unit is further configured to:
start a timer when the control circuit turns on the transistor; and
stop the timer after the predetermined time duration, and
wherein the blanking unit is further configured to refrain from preventing the control circuit from turning off the transistor after the leading-edge detection unit stops the timer.

5 . The control circuit of claim 1 ,
wherein the leading-edge detection unit comprises a capacitor, wherein the leading-edge detection unit is further configured to:
charge the capacitor during a rising phase of the leading-edge current spike, during which an electrical current through the transistor increases;
discharge the capacitor during a falling phase of the leading-edge current spike during which the electrical current through the transistor decreases; and
end the time interval when the electrical current through the transistor increases after the falling phase.

6 . The control circuit of claim 5 ,
wherein the control circuit is further configured to monitor a shunt voltage across a resistor electrically connected in series with the transistor, wherein the leading-edge detection unit is configured to charge the capacitor when the shunt voltage is greater than the voltage across the capacitor, wherein the leading-edge detection unit is configured to discharge the capacitor when the shunt voltage is less than the voltage across the capacitor, and wherein the leading-edge detection unit is further configured to end the time interval when the shunt voltage is greater than the voltage across the capacitor after discharging the capacitor.

7 . The control circuit of claim 6 ,
wherein the leading-edge detection unit further comprises at least one comparator and a first logic device, wherein the at least one comparator is configured to:
compare the shunt voltage and the voltage across the capacitor; and
generate an output signal based on comparing the shunt voltage and the voltage across the capacitor,
wherein the first logic device is configured to:
start the time interval when the control circuit turns on the transistor; and
end the time interval when the output signal indicates that the shunt voltage is greater than the voltage across the capacitor after the falling phase.

8 . The control circuit of claim 7 , wherein the leading-edge detection unit further comprises:
a second logic device configured to:
cause the leading-edge detection unit to begin charging the capacitor when the control circuit turns on the transistor;
cause the leading-edge detection unit to refrain from charging the capacitor when the output signal indicates that the shunt voltage is less than the voltage across the capacitor; and
a third logic device configured to:
cause the leading-edge detection unit to begin discharging the capacitor when the output signal indicates that the shunt voltage is less than the voltage across the capacitor; and
cause the leading-edge detection unit to refrain from discharging the capacitor when the output signal indicates that the shunt voltage is greater than the voltage across the capacitor.

9 . The control circuit of claim 5 , wherein the rising phase is a first rising phase, and wherein the leading-edge detection unit is further configured to:
turn on a first switch during the first rising phase to charge the capacitor; turn off the first switch during the falling phase; turn off a second switch during the first rising phase; turn on the second switch during the falling phase to discharge the capacitor; and turn off the first switch and the second switch during a second rising phase after the falling phase.

10 . The control circuit of claim 1 , wherein the leading-edge detection unit comprises a discharge switch configured to discharge the capacitor when the control circuit turns off the transistor.

11 . The control circuit of claim 1 , wherein the blanking unit is configured to prevent the control circuit from turning off the transistor during the time interval by at least causing the control circuit to deliver enabling control signals to the transistor during the time interval to cause the transistor to remain on.

12 . A method comprising:
detecting a time interval that corresponds to a leading-edge current spike through a transistor, wherein the time interval is independent of temperature; and refraining from turning off the transistor during the time interval.

13 . The method of claim 12 , wherein detecting the time interval comprises:
turning on the transistor; starting the time interval in response to turning on the transistor; and ending the time interval when the electrical current through the transistor increases after the falling phase.

14 . The method of claim 12 , further comprising:
turning on the transistor; starting a timer in response to turning on the transistor; stopping the timer after the predetermined time duration; ending the time interval in response to stopping the timer.

15 . The method of claim 12 , wherein detecting the time interval comprises:
charging a capacitor during a rising phase of the leading-edge current spike; discharging the capacitor during a falling phase of the leading-edge current spike; and ending the time interval at an end of the falling phase.

16 . The method of claim 15 , further comprising:
monitoring a shunt voltage across a resistor electrically connected in series with the transistor; and ending the time interval when the shunt voltage is greater than a voltage across the capacitor after discharging the capacitor, wherein charging the capacitor during the rising phase comprises charging the capacitor when the shunt voltage is greater than the voltage across the capacitor, and wherein discharging the capacitor during the falling phase comprises discharging the capacitor when the shunt voltage is less than the voltage across the capacitor.

17 . The method of claim 16 , further comprising:
turning on the transistor; comparing the shunt voltage and the voltage across the capacitor; generating an output signal based on comparing the shunt voltage and the voltage across the capacit

Assignees

• Infineon Technologies Austria Ag

Inventors

• Gong Xiaowu

Classifications

• H03K17/063 Primary

  in field-effect transistor switches · CPC title

• H03K5/1534 Primary

  Transition or edge detectors · CPC title

• H03K17/165

  by feedback from the output circuit to the control circuit · CPC title

• H03K17/0822

  in field-effect transistor switches · CPC title