Unified Addressable Memory

Patent metadata

Field	Value
Publication number	US-2019012484-A1
Application number	US-201615748893-A
Country	US
Kind code	A1
Filing date	Aug 25, 2016
Priority date	Sep 29, 2015
Publication date	Jan 10, 2019
Grant date	—

Abstract

In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

First claim

1 . A system comprising:
a non-volatile memory; and a system on a chip (SOC) coupled to the non-volatile memory, the SOC including:
one or more agents configured to generate read and write memory operations that address locations in the non-volatile memory, the locations forming a main memory in the system;
a link control circuit coupled to the one or more agents and configured to read and write the locations in the non-volatile memory responsive to the read and write memory operations; and
a cryptographic circuit coupled to the one or more agents and the link controller, wherein the cryptographic circuit is configured to encrypt data written to the locations in response to write memory operations from the one or more agents, and wherein the cryptographic circuit is configured to decrypt data read from the locations in response to read memory operations from the one or more agents, and wherein the cryptographic circuit is configured to employ one or more keys for the encryption or decryption, and wherein the SOC is configured to discard the one or more keys responsive to an event that causes the content of the locations to be declared lost to implement volatile behavior of the main memory.

2 . The system as recited in claim 1 wherein the non-volatile memory is divided into a first portion addressed by the read and write memory operations and a second portion that is defined to be a persistent storage, and wherein the persistent storage is managed by a file system executed on the SOC.

3 . The system as recited 1 wherein a portion of the non-volatile memory is persistent storage, and wherein the data in the persistent storage is encrypted using one or more second keys separate from the one or more keys, and wherein the SOC is configured to retain the one or more second keys in a metadata area of the non-volatile memory.

4 . The system as recited in claim 3 wherein the metadata area further stores initial vectors for use in the encryption or decryption of the data in the persistent storage.

5 . The system as recited in claim 4 wherein the SOC further comprises a metadata cache configured to cache data from the metadata stored in the metadata area.

6 . The system as recited in claim 1 wherein the content of the locations is declared lost responsive to a power down event in the system.

7 . The system as recited in claim 6 wherein the content of the locations is further declared lost responsive to one or more additional events in the system.

8 . The system as recited in claim 1 wherein the SOC is configured to generate the one or more keys randomly during a power up event in the system.

9 . The system as recited in claim 1 wherein a virtual address generated by one of the agents is translated through a first translation data structure to a first physical address and the first physical address is translated through a second translation data structure to a second physical address, and wherein a first page size in the first translation data structure differs from a second page size in the second translation data structure.

10 . The system as recited in claim 9 wherein the first page size is less than the second page size.

11 . The system as recited in claim 9 wherein the second page size matches a third page size implemented by the non-volatile memory.

12 . The system as recited in claim 9 further a cache control circuit configured to cache data from the non-volatile memory, wherein the cache is addressed by the first physical address.

13 . The system as recited in claim 9 further a cache control circuit configured to cache data from the non-volatile memory, wherein the cache is addressed by the second physical address.

14 . A method comprising:
generating read and write memory operations that address locations in a non-volatile memory by one or more agents in a system on a chip (SOC) , the locations forming a main memory in the system; reading and writing the locations in the non-volatile memory responsive to the read and write memory operations by a link control circuit coupled to the non-volatile memory and the one or more agents; encrypting data written to the locations in response to write memory operations from the one or more agents in a cryptographic circuit; decrypting data read from the locations in response to read memory operations from the one or more agents in the cryptographic circuits; and discarding one or more keys employed in the encrypting and decrypting responsive to an event that causes the content of the locations to be declared lost to implement volatile behavior of the main memory.

15 . The method as recited in claim 14 wherein generating the read and write memory operations includes generating a virtual address, and the method further comprises:
translating the virtual address through a first translation data structure to a first physical address; and
translating the first physical address through a second translation data structure to a second physical address, wherein a first page size in the first translation data structure differs from a second page size in the second translation data structure.

Assignees

• Apple Inc

Inventors

• Gulati Manu
• Sokol Jr Joseph
• Wilcox Jeffrey R
• Semeria Bernard J
• Smith Michael J

Classifications

• G06F12/1408

  by using cryptography (for digital transmission H04L9/00) · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title

• H04L2209/12

  Details relating to cryptographic hardware or logic circuitry · CPC title

• G06F21/72 Primary

  in cryptographic circuits · CPC title