Computer memory

Patent metadata

Field	Value
Publication number	US-2019005996-A1
Application number	US-201715640530-A
Country	US
Kind code	A1
Filing date	Jul 1, 2017
Priority date	Jul 1, 2017
Publication date	Jan 3, 2019
Grant date	—

Abstract

Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.

First claim

1 . A computer memory device, comprising:
a conductive structure; memory structures in communication with the conductive structure, the memory structures being disposed in a semiconductor composite material; an isolating material disposed between adjacent blocks of the memory structures; and a protective liner layer disposed between and in contact with the semiconductor composite material and the isolating material.

2 . The computer memory device of claim 1 , wherein the protective liner layer is in contact with a bottom surface of the isolating material.

3 . The computer memory device of claim 1 , wherein the isolating material comprises a wall configuration.

4 . The computer memory device of claim 1 , wherein the semiconductor composite material comprises a plurality of conductive layers, each conductive layer being separated from an adjacent conductive layer by an insulating layer.

5 . The computer memory device of claim 4 , wherein the conductive layers comprise polysilicon, tungsten, nickel, titanium, platinum, aluminum, gold, tungsten nitride, tantalum nitride, titanium nitride, or a combination thereof.

6 . The computer memory device of claim 4 , wherein the insulating layer comprises an oxide material, a nitride material, or a combination thereof.

7 . The computer memory device of claim 1 , wherein the protective liner layer is greater than or equal to 2 nm thick.

8 . The computer memory device of claim 7 , wherein the protective liner layer is less than or equal to 100 nm thick.

9 . The computer memory device of claim 1 , wherein the protective liner layer comprises an oxide material, a nitride material, or a combination thereof.

10 . The computer memory device of claim 1 , wherein the protective liner layer comprises SiNx, SiONx, AlOx, AlNx, AlONx, or a combination thereof.

11 . The computer memory device of claim 1 , wherein the isolating material comprises an oxide material, a metal material, or a combination thereof.

12 . The computer memory device of claim 1 , wherein the isolating material comprises tungsten, titanium nitride, polysilicon, or a combination thereof.

13 . The computer memory device of claim 1 , wherein staircase contacts in a staircase region are in communication with the conductive structure.

14 . A computing system, comprising:
a motherboard; and a computer memory device as in claim 1 operably coupled to the motherboard.

15 . The system of claim 14 , wherein the computing system comprises a desktop computer, a laptop, a tablet, a smartphone, a wearable device, a server, or a combination thereof.

16 . The system of claim 14 , further comprising a processor, a memory device, a heat sink, a radio, a slot, a port, or a combination thereof operably coupled to the motherboard.

17 . A method for isolating computer memory blocks in a memory array from one another, comprising:
forming an opening between adjacent blocks of memory structures; forming a protective liner layer on at least the memory structures; disposing isolating material in the opening and on the protective liner layer; removing the isolating material on the protective liner layer; and removing the protective liner layer on the memory structures.

18 . The method of claim 17 , wherein the opening comprises a slot configuration.

19 . The method of claim 17 , wherein the opening extends through a semiconductor composite material.

20 . The method of claim 17 , wherein the protective liner layer is greater than or equal to 2 nm thick.

21 . The method of claim 17 , wherein the protective liner layer comprises an oxide material, a nitride material, or a combination thereof.

22 . The method of claim 17 , wherein the protective liner layer comprises SiNx, SiONx, AlOx, AlNx, AlONx, or a combination thereof.

23 . The method of claim 17 , further comprising forming the protective liner layer in the opening.

24 . The method of claim 17 , wherein disposing the isolating material comprises a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a sputtering process, a thermal evaporation process, a plating process, or a combination thereof.

25 . The method of claim 17 , wherein the isolating material comprises an oxide material, a metal material, or a combination thereof.

26 . The method of claim 17 , wherein the isolating material comprises tungsten, titanium nitride, polysilicon, or a combination thereof.

27 . The method of claim 17 , wherein removing the isolating material comprises a chemical-mechanical planarization (CMP) process, a chemical polishing process, a mechanical planarization process, an etching process, a lift-off process, or a combination thereof.

28 . The method of claim 17 , wherein removing the protective liner layer comprises a chemical-mechanical planarization (CMP) process, a chemical polishing process, a mechanical planarization process, an etching process, a lift-off process, or a combination thereof.

29 . The method of claim 17 , wherein the isolating material and the protective liner layer are removed in the same process.

30 . The method of claim 17 , wherein forming the protective liner layer further comprises forming the protective liner layer in a staircase region.

Assignees

• Intel Corp

Inventors

• Larsen Christopher J
• Daycock David A
• Tao Qian
• Rathod Saniya
• Datta Devesh K
• Gowda Srivardhan
• Bhonsle Rithu K

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C8/12 Primary

  Group selection circuits, e.g. for memory block selection, chip selection, array selection · CPC title

• G11C16/06

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G06F3/0644

  Management of space entities, e.g. partitions, extents, pools · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title