Method for evaluating thermal effect and reducing thermal crosstalk of three-dimensional integrated resistive switching memory

Patent metadata

Field	Value
Publication number	US-2018366643-A1
Application number	US-201616064116-A
Country	US
Kind code	A1
Filing date	Aug 12, 2016
Priority date	Dec 24, 2015
Publication date	Dec 20, 2018
Grant date	—

Abstract

A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, including the following steps: Step 1: calculating the temperature distribution in the array through 3D Fourier heat conduction equation; Step 2, selecting a heat transfer mode; Step 3, selecting an appropriate array structure; Step 4, analyzing the effect of position of programming device in the array on the temperature; Step 5, analyzing the thermal crosstalk effect in the array; Step 6, evaluating thermal effects and thermal crosstalk; Step 7, changing the array structure or modify operating parameters based on the evaluation results to reduce the thermal crosstalk. According to the method of the present invention, the influence of the position of the device on the temperature is analyzed according to the heat transfer mode of the 3D RRAM array, the thermal effect and the thermal crosstalk are evaluated, and the appropriate array structure and operating parameters are selected according to the evaluation result, which effectively improves the thermal stability of the device.

First claim

1 . A method for evaluating the thermal effects of 3D RRAM arrays and reducing thermal crosstalk, the method comprising:
calculating the temperature distribution in the array through 3D Fourier heat conduction equation; selecting a heat transfer mode; selecting an appropriate array structure; analyzing the effect of position of programming device in the array on the temperature; analyzing the thermal crosstalk effect in the array; evaluating thermal effects and thermal crosstalk; changing the array structure or modifying operating parameters based on the evaluation results to reduce the thermal crosstalk.

2 . The method according to claim 1 , wherein the 3D Fourier heat conduction equation is

∇

k
th



∇
T

+

σ




∇
V



2

-

c



ρ


∂
T

∂
t

=
0

(
1
)

wherein k th represents thermal conductivity, T represents temperature, c represents heat capacity, ρ represents mass density of the material, t represents time, and σ represents electric conductance of material; preferably, the electric conductance of material changes with temperature, as shown in the following formula (2):

σ
=

σ
0

1
+

α


(

T
-

T
0

)

(
2
)

wherein α represents temperature coefficient of resistance, σ 0 represents the resistivity at room temperature T 0 ; the word line (WL) or bit line (BL) at the top and bottom of the array has an ideal heat dissipation package structure, the temperatures of top and bottom of the array are kept at room temperature T 0 in the calculation, as shown in equation (3):

T
-

T
0



|
BC


0.

(
3
)

3 . The method according to claim 1 , wherein in the heat transfer mode:
(i) heat is transferred between devices in same layer through the isolating dielectric material, or (ii) heat is transferred between RRAM devices in different layers in vertical direction.

4 . The method according to claim 1 , wherein the array structure is a 3D array of device units, each of which comprises one RRAM and one diode, wherein:
(i) the RRAM in one unit is connected to the diode in the adjacent unit via a WL/BL, or (ii) the diode in one unit is connected to the diode in the adjacent unit via a WL/BL.

5 . The method according to claim 2 , wherein, the thermal effect of the 3D integrated resistive switching device is analyzed by using the 3D Fourier heat conduction equation based on the physical parameters of conductive filaments of the RRAM device, diodes, and WL/BL, wherein the physical parameters are selected from any one of the following or any combinations thereof: radius, thickness, thermal conductivity, heat capacity, reference conductivity at room temperature, width, reset voltage, and room temperature.

6 . The method of claim 1 , wherein the thermal effects and thermal crosstalk in the device are estimated using transient temperature based on the Arrhenius law of the memory device.

7 . The method according to claim 1 , wherein changing the array structure or modifying operating parameters based on the evaluation results to reduce the thermal crosstalk further comprises: reducing the reset current or adopting a cycle-rehabilitate technique; the cycle-rehabilitate technique comprises after cr times cycles of RRAM arrays, all of the low resistance state devices in the array are erased and then a reprogramming operation is performed; and it is guaranteed that the resistance value can still distinguish between high and low resistance states in the degraded crosstalked RRAM device after cr times operations.

Assignees

• Inst Of Microelectronics Cas

Inventors

• Lu Nianduan
• Sun Pengxiao
• Li Ling
• Iiu Ming
• Liu Qi
• Lv Hangbing
• Long Shibing

Classifications

• G06F30/367 Primary

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• G11C7/04 Primary

  with means for avoiding disturbances due to temperature effects · CPC title

• G01N25/20

  by investigating the development of heat, i.e. calorimetry, e.g. by measuring specific heat, by measuring thermal conductivity (calorimeters per se G01K) · CPC title