Semiconductor device

Patent metadata

Field	Value
Publication number	US-2018366346-A1
Application number	US-201616061251-A
Country	US
Kind code	A1
Filing date	Dec 7, 2016
Priority date	Dec 11, 2015
Publication date	Dec 20, 2018
Grant date	—

Abstract

A semiconductor device according to the present invention includes a semiconductor chip having a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface, a conductive substrate onto which the semiconductor chip is die-bonded, a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate, and a resin package that seals at least the semiconductor chip and the conductive spacer.

First claim

1 . A semiconductor device comprising:
a semiconductor chip including a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface; a conductive substrate onto which the semiconductor chip is die-bonded; a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate; and a resin package that seals at least the semiconductor chip and the conductive spacer.

2 . The semiconductor device according to claim 1 , wherein the conductive spacer includes a columnar spacer integrally formed with the conductive substrate.

3 . The semiconductor device according to claim 2 , wherein the columnar spacer is formed into a rectangular parallelepiped shape having a side surface perpendicular to a surface of the conductive substrate.

4 . The semiconductor device according to claim 2 , wherein the columnar spacer is formed into a shape having a tapered side surface inclined with respect to the surface of the conductive substrate.

5 . The semiconductor device according to claim 2 , wherein the columnar spacer is formed into a shape having a side surface including a curved surface concaved toward the inside of the columnar spacer.

6 . The semiconductor device according to claim 1 , wherein the conductive spacer is bonded to the conductive substrate via a second bonding material.

7 . The semiconductor device according to claim 6 , wherein the conductive spacer and the conductive substrate are formed of materials different from each other.

8 . A semiconductor device comprising:
a semiconductor chip including a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface; a conductive substrate onto which the semiconductor chip is die-bonded; a conductive spacer that is a hollow conductive spacer formed by selectively projecting a part of the conductive substrate and has a planar area smaller than that of the first electrode; and a resin package that seals at least the semiconductor chip and the conductive spacer.

9 . The semiconductor device according to claim 1 , wherein
the semiconductor chip has, in a surface portion of the semiconductor layer on the first surface side, a first conductivity type first impurity region electrically connected to the first electrode, and a second conductivity type second impurity region exposed to the outer side of the first electrode, and the second impurity region has a portion that becomes the same potential as that of the second electrode when a reverse voltage is applied between the first electrode and the second electrode.

10 . The semiconductor device according to claim 1 , comprising: a bonding material that is provided between the conductive spacer and the first electrode of the semiconductor chip, and has a projecting portion projecting from the conductive spacer and fitting inside the first electrode.

11 . The semiconductor device according to claim 1 , further comprising: a protective insulation film that is formed in contact with at least a peripheral edge portion of the first electrode, and covers an area from the peripheral edge of the first electrode to the end surface of the semiconductor layer.

12 . The semiconductor device according to claim 1 , wherein
a part of the resin package enters a space between a portion of the semiconductor chip on an outer side of the conductive spacer and the conductive substrate, and when a withstand voltage of the semiconductor device is V B1 (V), a withstand voltage of the resin package per unit length is V B2 (V/mm), and a height distance between the semiconductor chip and the conductive substrate is H, the height H exceeds V B1 /V B2 .

13 . The semiconductor device according to claim 9 , wherein
a part of the resin package enters a space between a portion of the semiconductor chip on an outer side of the conductive spacer and the conductive substrate, and when a withstand voltage of the semiconductor device is V B1 (V), a withstand voltage of the resin package per unit length is V B2 (V/mm), and a distance between a peripheral surface of the conductive spacer and a peripheral surface of the second impurity region is L, the distance L exceeds V B1 /V B2 .

14 . The semiconductor device according to claim 1 , wherein the conductive spacer is made of Cu or an alloy containing Cu, or a metal whose surface is plated with Cu.

15 . The semiconductor device according to claim 1 , wherein the conductive substrate includes an island portion on which the semiconductor chip is disposed, and a terminal portion extending from the island portion.

16 . The semiconductor device according to claim 9 , wherein the semiconductor chip includes an active region in which a plurality of transistors are formed in a surface portion of the semiconductor layer, and an outer peripheral region in which a protection element is formed so as to surround the active region.

17 . The semiconductor device according to claim 1 , wherein the semiconductor layer is a wide bandgap type semiconductor layer.

18 . A power converter using the semiconductor device according to claim 1 as a bidirectional switch circuit.

19 - 53 . (canceled)

Assignees

• Rohm Co Ltd

Inventors

• Mori Seigo
• Aketa Masatoshi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/07552

  changes in structures or sizes · CPC title

• H10W72/926

  Multiple bond pads having different sizes · CPC title