Asynchronous/synchronous interface

Patent metadata

Field	Value
Publication number	US-2018366166-A1
Application number	US-201816110294-A
Country	US
Kind code	A1
Filing date	Aug 23, 2018
Priority date	Jun 2, 2008
Publication date	Dec 20, 2018
Grant date	—

Abstract

The present disclosure includes methods, and circuits, for operating a memory device. One method embodiment for operating a memory device includes controlling data transfer through a memory interface in an asynchronous mode by writing data to the memory device at least partially in response to a write enable signal on a first interface contact, and reading data from the memory device at least partially in response to a read enable signal on a second interface contact. The method further includes controlling data transfer in a synchronous mode by transferring data at least partially in response to a clock signal on the first interface contact, and providing a bidirectional data strobe signal on an interface contact not utilized in the asynchronous mode.

First claim

1 .- 20 . (canceled)

21 . An apparatus, comprising:
a memory interface including: a first memory interface contact; a second memory interface contact; and a third memory interface contact; wherein the memory interface is configured to:
switchably operate in either an asynchronous mode or a synchronous mode; and
operate in the synchronous mode utilizing one additional contact of the memory interface than a quantity of contacts utilized in the asynchronous mode.

22 . The apparatus of claim 21 , wherein the one additional contact of the memory interface is configured to send and receive a bidirectional data strobe signal.

23 . The apparatus of claim 21 , wherein the memory interface is configured to utilize two signals complementary to memory interface control signals utilized in the asynchronous mode.

24 . The apparatus of claim 23 , wherein one of the two signals complementary to memory interface control signals utilized in the synchronous mode includes a complementary clock signal.

25 . The apparatus of claim 21 , wherein the memory interface is configured to receive a signal on the first memory interface contact as a write enable signal in the asynchronous mode and as a clock signal in the synchronous mode.

26 . The apparatus of claim 21 , wherein the memory interface is configured to receive a signal on the second memory interface contact as a read enable signal in the asynchronous mode and as a write/read signal in the synchronous mode.

27 . The apparatus of claim 21 , wherein the memory interface is configured to detect for a clock signal on the first memory interface contact at least partially in response to detection of a chip enable signal on a different memory interface contact.

28 . An apparatus, comprising:
a memory device; and control circuitry configured to:
write data to the memory device in an asynchronous mode in response to a write enable signal received on a first interface contact; and
transfer data to the memory device in a synchronous mode in response to a clock signal received on the first interface contact and a signal received on an interface contact not utilized in the asynchronous mode.

29 . The apparatus of claim 28 , wherein the signal on the interface contact not utilized in the asynchronous mode is a bidirectional data strobe signal.

30 . The apparatus of claim 28 , wherein the control circuitry is configured to respond to an unasserted state of a read enable signal as a write enable signal while in the synchronous mode.

31 . The apparatus of claim 28 , wherein a quantity of interface contacts utilized in the synchronous mode is only one more than the quantity of interface contacts utilized in the asynchronous mode.

32 . The apparatus of claim 28 , wherein the control circuitry is configured to control switching between the asynchronous mode and the synchronous mode responsive to a mode selection signal.

33 . The apparatus of claim 28 , wherein the control circuitry is configured to control switching between the asynchronous mode and the synchronous mode responsive to the clock signal no longer being a periodic signal corresponding to a predetermined number of clock cycles.

34 . The apparatus of claim 28 , wherein the control circuitry is configured to switch between the asynchronous mode and the synchronous mode responsive to a command received by the memory device.

35 . A method, comprising:
switchably operating a memory interface in a synchronous mode and an asynchronous mode, wherein operating the memory interface in the synchronous mode utilizes one additional contact of the memory interface than a quantity of contacts utilized in the asynchronous mode.

36 . The method of claim 35 , further comprising:
operating the memory interface in the asynchronous mode utilizing a write enable signal on a first contact of the memory interface; and operating the memory interface in the synchronous mode utilizing a clock signal on the first contact of the memory interface.

37 . The method of claim 35 , further comprising:
operating the memory interface in the asynchronous mode utilizing a read enable signal on a second contact of the memory interface; and operating the memory interface in the synchronous mode utilizing a read-write signal on the second contact of the memory interface.

38 . The method of claim 35 , further comprising powering up the memory interface in the synchronous mode.

39 . The method of claim 35 , further comprising powering up the memory interface in the asynchronous mode.

40 . The method of claim 35 , further comprising switching from the asynchronous mode to the synchronous mode at least partially in response to detection of a clock signal on a memory interface contact of the memory interface.

Assignees

• Micron Technology Inc

Inventors

• Nobunaga Dean K
• Lee June
• Chen Chih Liang

Classifications

• G11C14/0009

  in which the volatile element is a DRAM cell · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title