Gate Driving Circuit and Display Device Using the Same

Patent metadata

Field	Value
Publication number	US-2018366066-A1
Application number	US-201715818358-A
Country	US
Kind code	A1
Filing date	Nov 20, 2017
Priority date	Jun 14, 2017
Publication date	Dec 20, 2018
Grant date	—

Abstract

A display device according to an embodiment of the present disclosure comprises a display panel including a display area having a plurality of pixels connected to a plurality of gate lines, a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines, and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area in which a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies. Therefore, the load applied to the output node of the gate driving circuit is uniformly adjusted so that a screen abnormality of the display device may be suppressed.

First claim

What is claimed is:

1 . A display device, comprising:
a display panel including a display area having a plurality of pixels connected to a plurality of gate lines; a gate driving circuit in a non-display area adjacent to the display area and including a plurality of stages supplying a gate signal to the plurality of gate lines; and an auxiliary load connected to at least one stage of the plurality of stages in the non-display area, wherein a number of the plurality of pixels which are connected to at least two gate lines among the plurality of gate lines varies.

2 . The display device according to claim 1 , wherein the auxiliary load includes a capacitor and a resistor and is located between the display area and the at least one stage among the plurality of stages or at an end of the gate line.

3 . The display device according to claim 1 , wherein a smaller the number of the plurality of pixels connected to the plurality of gate lines, a larger the auxiliary load.

4 . The display device according to claim 1 , wherein the auxiliary load includes at least two electrodes, and the at least two electrodes are overlapped with each other.

5 . The display device according to claim 4 , wherein one electrode of the at least two electrodes is connected to an output node of a stage in which the auxiliary load is disposed and the gate line, and
a constant voltage is applied to another electrode of the at least two electrodes so that the at least two electrodes form a capacitor.

6 . The display device according to claim 1 , wherein each of the plurality of stages includes a first transistor and a second transistor which are connected in series,
the first transistor and the second transistor are connected to an output node of a stage having the first transistor and the second transistor, and the auxiliary load is connected to the output node and located between the output node and pixels corresponding to each of the plurality of stages, or the auxiliary load is located at an end of the gate line.

7 . The display device according to claim 6 , wherein a size of an active layer of any one of the first transistor and the second transistor included in the stages corresponding to a heterogeneous structure area of the display panel is smaller than a size of an active layer of any one of the first transistor and the second transistor included in the stages corresponding to a normal structure area of the display panel.

8 . The display device according to claim 7 , wherein a width of the active layer of any one of the first transistor and the second transistor in each of the plurality of stages corresponding to the heterogeneous structure area is 80 μm or larger and 240 μm or smaller.

9 . The display device according to claim 1 , wherein the plurality of stages includes emission stages which are connected to the plurality of gate lines, respectively,
a pixel driving circuit which drives the plurality of pixels includes a driving transistor and an emitting transistor which controls emission of the plurality of pixels; and the emitting transistor is turned on while the plurality of pixels emits light.

10 . A display device, comprising:
a display panel including a display area having a normal structure area and a heterogeneous structure area, and a non-display area adjacent to the display area, wherein the display panel includes: gate lines; a plurality of pixels connected to the gate lines; a gate driving circuit having stages supplying a gate signal to the gate lines in the non-display area; and a dummy load connected to stages connected to the plurality of pixels in the heterogeneous structure area, the dummy load being in the non-display area.

11 . The display device according to claim 10 , wherein the heterogeneous structure area includes a heterogeneous structure which is not defined as a polygon, and
the dummy load is adjacent to the plurality of pixels according to a shape of the heterogeneous structure.

12 . The display device according to claim 10 , wherein the stages include a first transistor and a second transistor which are connected in series,
the gate signal is output from a node which is shared by the first transistor and the second transistor, and a size of an active layer of any one of the first transistor and the second transistor included in the stages corresponding to the heterogeneous structure area of the display panel is smaller than a size of an active layer of any one of the first transistor and the second transistor included in the stages corresponding to the normal structure area of the display panel.

13 . The display device according to claim 12 , wherein a width of the active layer of any one of the first transistor and the second transistor in each of the plurality of stages corresponding to in the heterogeneous structure area is 80 μm or larger and 240 μm or smaller.

14 . The display device according to claim 10 , wherein the display panel includes a driving transistor and a data routing line,
the driving transistor and the data routing line include an active layer, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode, and the dummy load includes a capacitor having two or more electrodes among the active layer, the first gate electrode, the second gate electrode, the source electrode, and the drain electrode.

15 . The display device according to claim 14 , wherein the display panel includes:
a first insulating layer between the active layer and the first gate electrode; a second insulating layer between the first gate electrode and the second gate electrode; and a third insulating layer between the second gate electrode and the source electrode or the drain electrode, wherein a thickness of the first insulating layer is larger than a thickness of the second insulating layer and the thickness of the first insulating layer is smaller than a thickness of the third insulating layer.

16 . The display device according to claim 14 , wherein the capacitor includes a first electrode, a second electrode, and a third electrode,
the first electrode is the active layer, the second electrode is the first gate electrode or the second gate electrode, and the third electrode is the source electrode or the drain electrode, and the first electrode and the third electrode are connected to each other, or the first electrode is the first gate electrode, the second electrode is the second gate electrode, and the third electrode is the source electrode or the drain electrode, and the second electrode and the third electrode are connected to each other.

17 . The display device according to claim 14 , wherein the active layer in the dummy load is doped to be conductivized.

18 . A display device, comprising:
a display area including a pixel array having a plurality of pixels connected to a plurality of gate lines; a non-display area being adjacent to the display area, the non-display area having a gate driving circuit; and a dummy load connected to an output node of the gate driving circuit to improve an erroneous output phenomenon of the gate driving circuit due to a load imbalance of the display area.

19 . The display device according to claim 18 , wherein the load imbalance of the display area is caused in accordance with a change in a number of pixels connected to the gate lines, and
the dummy load disposed in an area where the load imbalance is generated varies according to the change in the number of pixels.

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Assignees

• Lg Display Co Ltd

Inventors

• Kim Jiyun
• JANG ChangJae
• Chin Kyungah
• Kim Jinhwan
• Park Jongchan
• Um Hyunchul
• Seong Eunkyung

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G3/3266 Primary

  Details of drivers for scan electrodes · CPC title