Implementing synchronous triggers for waveform capture in an FPGA prototyping system
US-9495492-B1 · Nov 15, 2016 · US
US2018364282A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018364282-A1 |
| Application number | US-201816005763-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 12, 2018 |
| Priority date | Jun 14, 2017 |
| Publication date | Dec 20, 2018 |
| Grant date | — |
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The present invention provides a method and apparatus for automatically adjusting the hold-off time of a DSO based on real-time cycle measurements of the system trigger signal: obtaining a cycle sequence by measuring the system trigger signal, the maximum cycle and minimum cycle, then judging the difference of the maximum cycle and minimum cycle: if the difference is greater than a threshold set by user, setting the hold-off time to the maximum cycle, the minimum cycle or the median cycle, then returning; otherwise terminating the adjustment of the hold-off time. At this point, the hold-off time is correctly set. Therefore, the present invention reduces the complexity and time consumption of the hold-off adjustment, and allows the test signal to be quickly and stably displayed on screen of DSO, meanwhile, which makes the trigger adjustment of DSO more convenient.
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What is claimed is: 1 . A method for automatically adjusting the hold-off time of a DSO, comprising: (1) generating a synchronizing trigger signal according to the characteristics of the test signal, and setting the hold-off time to zero or the minimum value to which the hold-off time can be set; (2) measuring a system trigger signal in real time to obtain a cycle sequence C 1 , C 2 , . . . , C n , wherein the system trigger signal is obtained by holding off the synchronizing trigger signal according to the hold-off time; (3) detecting the cycle sequence C 1 , C 2 , . . . , C n to obtain a maximum cycle and a minimum cycle, where the maximum cycle is denoted by C max C max , the minimum cycle is denoted by C max C min ; (4) judging the difference C max −C min : if the difference C max −C min is greater than a threshold set by user, setting the hold-off time to the maximum cycle C max , the minimum cycle C min or the median cycle (C max −+C min )/2, and then returning to step (2); otherwise, the difference C max −C min is not greater than a threshold set by user, terminating the adjustment of the hold-off time. At this point, the hold-off time is correctly set. 2 . The method for automatically adjusting the hold-off time of a DSO as recited in claim 1 further, comprising setting an upper limit to the number of iterations, i.e. the number of returning to step (2), when the upper limit is reached, terminating the adjustment of the hold-off time. 3 . A apparatus for automatically adjusting the hold-off time of a DSO, comprising: a trigger module for generating a synchronizing trigger signal according to the characteristics of the test signal; a hold-off module for obtaining a system trigger signal by holding off the synchronizing trigger signal according to the hold-off time, where the system trigger signal is outputted to the acquisition module to control the acquisition of the test signal; wherein further comprising: a cycle measurement and judgment module for measuring the system trigger signal in real time to obtain a cycle sequence C 1 , C 2 , . . . , C n , detecting the cycle sequence C 1 , C 2 , . . . , C n to obtain a maximum cycle and a minimum cycle, where the maximum cycle is denoted by C max , the minimum cycle is denoted by C min , and judging the difference C max −C min : if the difference C max −C min is greater than a threshold set by user, setting the hold-off time to the maximum cycle C max , minimum cycle C min or the median cycle (C max +C min )/2, and then continuing to measure, detect, and judge, until the difference C max −C min is not greater than a threshold set by user or the number of iterations reaches the upper limit.
for triggering, synchronisation · CPC title
in numerical form · CPC title
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