Memory device including otp memory cell and program method thereof

Patent metadata

Field	Value
Publication number	US-2018358369-A1
Application number	US-201715848988-A
Country	US
Kind code	A1
Filing date	Dec 20, 2017
Priority date	Jun 12, 2017
Publication date	Dec 13, 2018
Grant date	—

Abstract

A memory device includes a main one-time programmable (OTP) memory cell connected to a main word line and a main bit line; a redundant OTP memory cell connected to a redundant word line and a redundant bit line; and an input/output circuit configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate the main bit line and the redundant bit line and form a first program current path to the main bit line and a second program current path to redundant bit line, wherein the first program current path and the second program current path are independent from each other.

First claim

What is claimed is:

1 . A memory device comprising:
a main one-time programmable (OTP) memory cell connected to a main word line and a main bit line; a redundant OTP memory cell connected to a redundant word line and a redundant bit line; and an input/output circuit configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate the main bit line and the redundant bit line and form a first program current path to the main bit line and a second program current path to redundant bit line, wherein the first program current path and the second program current path are independent from each other.

2 . The memory device of claim 1 , wherein the input/output circuit is further configured to, during the program operation, the main word line and the redundant word line are selected together, the main bit line and the redundant bit line are selected together, and a program voltage is simultaneously applied to the main word line and the redundant word line, at a same time.

3 . The memory device of claim 1 , wherein the input/output circuit comprises:
a first current source circuit configured to provide a first program current via the first program current path to the main bit line; and a second current source circuit configured to provide a second program current via the second program current path to the redundant bit line.

4 . The memory device of claim 3 , wherein the input/output circuit further comprises:
a first switch configured to connect the first current source circuit to the main bit line to form the first program current path in response to a write enable signal; and a second switch configured to connect the second current source circuit to the redundant bit line to form the second program current path in response to the write enable signal.

5 . The memory device of claim 4 , wherein the input/output circuit further comprises:
a sense amplifier configured to sense data programmed in the main OTP memory cell and the redundant OTP memory cell; a third switch configured to connect the sense amplifier and the main bit line in response to a read enable signal; and a fourth switch configured to the sense amplifier and the redundant bit line in response to the read enable signal.

6 . The memory device of claim 5 , wherein the third switch and the fourth switch are turned off to electrically separate the main bit line and the redundant bit line during the program operation.

7 . The memory device of claim 1 , further comprising:
a main row decoder configured to select the main word line in response to a row address; and a redundant row decoder configured to select the redundant word line in response to the row address.

8 . The memory device of claim 1 , further comprising a voltage generator configured to provide a program voltage and a read voltage to each of the main word line and the redundant word line.

9 . The memory device of claim 8 , wherein the voltage generator comprises:
a charge pump configured to generate the program voltage; a voltage regulator configured to generate the read voltage; and a switch circuit configured to transfer the program voltage or the read voltage to the main word line or the redundant word line depending on an operation mode.

10 . The memory device of claim 9 , wherein the switch circuit comprises:
a first voltage switch configured to transfer the program voltage that is generated by the charge pump to a first node depending on the operation mode; a second voltage switch configured to transfer the read voltage that is generated by the voltage regulator to the first node depending on the operation mode; a third voltage switch configured to electrically connect the first node to the main word line in response to a first selection signal; and a fourth voltage switch configured to electrically connect the first node to the redundant word line in response to a second selection signal.

11 . The memory device of claim 1 , wherein the main word line comprises a program word line and a selection word line, and
wherein the main OTP memory cell comprises: a selection transistor comprising a first gate connected to the selection word line and one end connected to the main bit line; and a fuse transistor comprising a second gate connected to the program word line and a source connected to an opposite end of the selection transistor.

12 . A program method of a memory device which comprises a main one-time programmable (OTP) memory cell and a redundant OTP memory cell, the program method comprising:
receiving an address for selecting the main OTP memory cell and the redundant OTP memory cell together; generating a program voltage to be supplied to a main word line of the main OTP memory cell and a redundant word line of the redundant OTP memory cell; electrically separating a main bit line to which the main OTP memory cell is connected and a redundant bit line to which the redundant OTP memory cell is connected; and supplying the program voltage to the main word line of the main OTP memory cell and the redundant word line of the redundant OTP memory cell and forming a first program current path to the main bit line and a second program current path to the redundant bit line, wherein the first program current path and the second program current path are independent from each other.

13 . The program method of claim 12 , wherein the program voltage is simultaneously supplied to the main OTP memory cell and the redundant OTP memory cell.

14 . The program method of claim 12 , further comprising:
providing a first program current generated by a first current source circuit to the main bit line via the first program current path; and providing a second program current generated by a second current source circuit to the redundant bit line via the second program current path.

15 . The program method of claim 12 , wherein the main bit line and the redundant bit line are electrically connected to each other during a read operation.

16 . A memory device comprising:
a main cell array comprising a plurality of main one-time programmable (OTP) memory cells; a redundant cell array comprising a plurality of redundant OTP memory cells; and an input/output circuit comprising a first current source circuit and a second current source circuit, the input/output circuit being configured to electrically connect the first current source circuit to a main OTP memory cell selected from among the plurality of main OTP memory cells and the second current source circuit to a redundant OTP memory cell selected from among the plurality of redundant OTP memory cells, depending on an operation mode.

17 . The memory device of claim 16 , wherein in a program operation to program the main OTP memory cell and the redundant OTP memory cell, a program voltage is simultaneously applied to a main word line of the main OTP memory cell that is selected and a redundant word line of the redundant OTP memory cell that is selected.

18 . The memory device of claim 16 , wherein the input/output circuit is further configured to, during a program operation to program the main OTP memory cell and the redundant OTP memory cell, electrically separate a main bit line to which the main OTP memory cell is connected and a redundant bit line to which the redundant OTP memory cell is connected, and
wherein during the program operation, the main bit line and the redundant bit line are specified by a same column address.

19 . The memor

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sang-Seok

Classifications

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title

• G11C11/005

  comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells · CPC title

• G11C29/846

  by choosing redundant lines at an output stage · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C17/08 Primary

  using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) · CPC title