Methods and systems for background calibration of multi-phase parallel receivers

Patent metadata

Field	Value
Publication number	US-2018351769-A1
Application number	US-201815992105-A
Country	US
Kind code	A1
Filing date	May 29, 2018
Priority date	May 31, 2017
Publication date	Dec 6, 2018
Grant date	—

Abstract

Methods and systems are described for receiving a plurality of signals in a signaling interval at a multi-input comparator (MIC), and responsively generating an analog linear combination of the received signals, amplifying the analog linear combination of the received signals using an integration stage, receiving the amplified differential voltage at two multi-phase receivers, each multi-phase receiver comprising one or more processing slices, each multi-phase receiver operating in a multi-phase processing path for processing the amplified differential voltage, wherein processing the amplified differential voltage includes generating output data decisions and phase-error information using a first multi-phase receiver of the two multi-phase receivers and selectively adjusting local speculative decision feedback equalization (DFE) slicing offsets of a second multi-phase receiver of the two multi-phase receivers according to the output data decisions generated by the first multi-phase receiver.

First claim

1 . An apparatus comprising:
a multi-input comparator (MIC) configured to receive a plurality of signals in a signaling interval from wires of a multi-wire bus and to responsively generate an analog linear combination of the received signals; an integration stage configured to receive the analog linear combination of the received signals and to responsively amplify the received analog linear combination to generate an amplified differential voltage; and two multi-phase receivers connected in parallel to the integration stage, each multi-phase receiver comprising one or more processing slices, each multi-phase receiver configured to receive the amplified differential voltage and to operate in a multi-phase processing path for processing the amplified differential voltage, the two multi-phase receivers comprising:
a first multi-phase receiver of the two multi-phase receivers configured to process the amplified differential voltage to generate output data decisions and phase-error information; and
a second multi-phase receiver selectively configured to adjust local speculative decision feedback equalization (DFE) slicing offsets according to the output data decisions generated by the first multi-phase receiver.

2 . The apparatus of claim 1 , wherein the two multi-phase receivers comprise a symmetrical circuit layout.

3 . The apparatus of claim 1 , wherein the integration stage is configured to perform pre-cursor compensation on the received analog linear combination to generate the amplified differential voltage by applying at least one DFE correction value to the received analog linear combination.

4 . The apparatus of claim 1 , wherein each processing slice of the one or more processing slices of the first multi-phase receiver is configured to sample the received amplified differential voltage according to a respective phase of a plurality of phases of a sampling clock.

5 . The apparatus of claim 4 , wherein each processing slice is configured to (i) receive an output data decision from and to (ii) provide an output data decision to respective processing slices receiving adjacent respective phases of the plurality of phases of the sampling clock.

6 . The apparatus of claim 4 , wherein the at least one processing slice of the second multi-phase receiver is configured to receive at least one of the phases of the plurality of phases of the sampling clock.

7 . The apparatus of claim 1 , wherein the second multi-phase receiver is selectively configurable to utilize at least one processing slice of the one or more processing slices to make eye-scope measurements.

8 . The apparatus of claim 7 , wherein the at least one processing slice is configured to receive an eye scope clock signal generated by a phase interpolator operating on at least two phases of a plurality of phases of a sampling clock.

9 . The apparatus of claim 8 , wherein the phase interpolator is configured to incrementally rotate a phase of the eye scope clock signal to make the eye-scope measurements corresponding to eye width.

10 . The apparatus of claim 7 , wherein the at least one processing slice is configured to adjust slicer offset values and to sample the amplified differential voltage to make eye-scope measurements corresponding to eye height.

11 . A method comprising:
receiving a plurality of signals in a signaling interval at a multi-input comparator (MIC), and responsively generating an analog linear combination of the received signals; amplifying the analog linear combination of the received signals using an integration stage; receiving the amplified differential voltage at two multi-phase receivers, each multi-phase receiver comprising one or more processing slices, the two multi-phase receivers operating in a multi-phase processing path for processing the amplified differential voltage, wherein processing the amplified differential voltage comprises: generating output data decisions and phase-error information using a first multi-phase receiver of the two multi-phase receivers; and selectively adjusting local speculative decision feedback equalization (DFE) slicing offsets of a second multi-phase receiver of the two multi-phase receivers according to the output data decisions generated by the first multi-phase receiver.

12 . The method of claim 11 , wherein the two multi-phase receivers have a symmetrical circuit layout.

13 . The method of claim 11 , further comprising performing pre-cursor compensation on the received analog linear combination to generate the amplified differential voltage by applying a DFE correction value to the received analog linear combination via the integration stage.

14 . The method of claim 11 , wherein each processing slice of the one or more processing slices of the first multi-phase receiver processes the amplified differential voltage by sampling the amplified differential voltage according to a respective phase of a plurality of phases of a sampling clock.

15 . The method of claim 14 , wherein each processing slice (i) receives an output data decision from and (ii) provides an output data decision to respective processing slices receiving adjacent respective phases of the plurality of phases of the sampling clock.

16 . The method of claim 14 , further comprising providing at least one of the phases of the plurality of phases of the sampling clock to at least one processing slice of the one or more processing slices of the second multi-phase receiver.

17 . The method of claim 11 , further comprising selectively configuring the second multi-phase receiver to utilize at least one processing slice of the one or more processing slices to make eye-scope measurements.

18 . The method of claim 17 , further comprising providing an eye scope clock signal to the at least one processing slice, the eye scope clock signal generated by a phase interpolator operating on at least two phases of a plurality of phases of a sampling clock.

19 . The method of claim 18 , further comprising incrementally rotating a phase of the eye scope clock signal to make eye-scope measurements corresponding to eye width.

20 . The method of claim 17 , further comprising adjusting slicer offset values of the at least one processing slice and sampling the amplified differential voltage to make eye-scope measurements corresponding to eye height.

Assignees

• Kandou Labs SA

Inventors

• Tajalli Armin
• Simpson Richard

Classifications

• H04L5/0007

  the frequencies being orthogonal, e.g. OFDM(A) or DMT · CPC title

• H04L25/03057

  with a recursive structure (H04L25/03031 takes precedence) · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H03L7/06

  using a reference signal applied to a frequency- or phase-locked loop · CPC title

• H04L25/0272 Primary

  Arrangements for coupling to multiple lines, e.g. for differential transmission · CPC title