Control area network (can) transceivers with automatic polarity detection

Patent metadata

Field	Value
Publication number	US-2018351765-A1
Application number	US-201715854583-A
Country	US
Kind code	A1
Filing date	Dec 26, 2017
Priority date	May 31, 2017
Publication date	Dec 6, 2018
Grant date	—

Abstract

Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

First claim

1 . A control area network (CAN) bus integrated circuit comprising:
CAN bus high and low pins; a receive data pin; a first CAN bus transceiver having normal and standby modes, the first CAN bus transceiver including:
high and low CAN bus connections, the first CAN bus transceiver high CAN bus connection connected to the high CAN bus pin and the first CAN bus transceiver low CAN bus connection connected to the low CAN bus pin;
a first receiver having high and low inputs and an output, the first receiver high input connected to the high CAN bus connection and the first receiver low input connected to the low CAN bus connection;
a first low power receiver having high and low inputs and an output, the first low power receiver high input connected to the high CAN bus connection and the first low power receiver low input connected to the low CAN bus connection;
a first wake up logic monitor having an input coupled to the first low power receiver output and having an output, a wake up indication being provided on the output when the first wake up logic monitor detects a wake up pattern on the CAN bus;
a second CAN bus transceiver having normal and standby modes, the second CAN bus transceiver including:
high and low CAN bus connections, the second CAN bus transceiver high CAN bus connection connected to the low CAN bus pin and the second CAN bus transceiver low CAN bus connection connected to the high CAN bus pin;
a second receiver having high and low inputs and an output, the receiver high input connected to the low CAN bus connection and the receiver low input connected to the high CAN bus connection;
a second low power receiver having high and low inputs and an output, the second low power receiver high input connected to the low CAN bus connection and the second low power receiver low input connected to the high CAN bus connection;
a second wake up logic monitor having an input coupled to the second low power receiver output and having an output, a wake up indication being provided on the output when the second wake up logic monitor detects a wake up pattern on the CAN bus;
detection logic coupled to the first wake up logic monitor output and the second wake up logic monitor output to detect which of the first wake up logic monitor and the second wake up logic monitor provides a wake up indication and having an output of the detection; direction logic coupled to the detection logic and the first and second CAN bus transceivers to use the output of the detection logic to place the one of the first and second CAN bus transceivers that provided the wake up indication from the first or second wake up logic monitor into normal mode and to place the other of the first and second CAN bus transceivers into standby mode; and output circuitry coupled to the receive data pin, to the direction logic and to the outputs of the first and second receivers and providing a output CAN bus receive data signal from the one of the first and second CAN bus transceivers in normal mode to the receive data pin.

2 . The CAN bus integrated circuit of claim 1 , further comprising a transmit data pin coupled to the first and second CAN bus transceivers, and
wherein the first CAN bus transceiver further includes a first driver, the first driver having an input coupled to the transmit data pin and high and low outputs, the first driver high output connected to the high CAN bus connection and the first driver low output connected to the low CAN bus connection, and wherein the second CAN bus transceiver further includes a second driver, the second driver having an input coupled to the transmit data pin and high and low outputs, the second driver high output connected to the low CAN bus connection and the second driver low output connected to the high CAN bus connection.

3 . The CAN bus integrated circuit of claim 1 , further comprising an automatic polarity enable pin for receiving an automatic polarity selection signal and coupled to the direction logic,
wherein the direction logic places the first CAN bus transceiver in normal mode and the second CAN bus transceiver in standby mode when the automatic polarity enable signal indicates that automatic polarity enable is disabled.

4 . The CAN bus integrated circuit of claim 1 , wherein the detection logic includes a first flip-flop and a second flip-flop, the first flip-flop receiving the first wake up logic monitor output and the second flip-flop receiving the second wake up logic monitor output.

5 . The CAN bus integrated circuit of claim 1 , wherein first CAN bus transceiver further includes first overtemperature and first under voltage detection modules providing outputs,
wherein second CAN bus transceiver further includes second overtemperature and second under voltage detection modules providing outputs, and wherein the direction logic is coupled to the first overtemperature and first under voltage detection modules outputs and the second overtemperature and second under voltage detection modules outputs and places the first CAN bus transceiver into standby when either of the first overtemperature or first under voltage detection modules outputs indicates an error and places the second CAN bus transceiver into standby when either of the second overtemperature or second under voltage detection modules outputs indicates an error.

6 . The CAN bus integrated circuit of claim 1 , further comprising an external standby pin coupled to the direction logic and for receiving an external standby signal,
wherein the direction logic places the one of the first and second CAN bus transceivers in normal mode into standby mode when the external standby signal is asserted.

7 . The CAN bus integrated circuit of claim 1 , wherein the first low power receiver is not placed in standby when the first CAN bus transceiver is in standby mode and the second low power receiver is not placed in standby when the second CAN bus transceiver is in standby mode.

8 . A control area network (CAN) bus controller comprising:
a microcontroller; a CAN bus connector for receiving CAN bus high and low lines; one of a controller input or a controller output coupled to the microcontroller; and a CAN bus integrated circuit coupled to the microcontroller and to the CAN bus connector, the CAN bus integrated circuit including:
CAN bus high and low pins coupled to the CAN bus connector;
a receive data pin coupled to the microcontroller;
a first CAN bus transceiver having normal and standby modes, the first CAN bus transceiver including:
high and low CAN bus connections, the first CAN bus transceiver high CAN bus connection connected to the high CAN bus pin and the first CAN bus transceiver low CAN bus connection connected to the low CAN bus pin;
a first receiver having high and low inputs and an output, the first receiver high input connected to the high CAN bus connection and the first receiver low input connected to the low CAN bus connection;
a first low power receiver having high and low inputs and an output, the first low power receiver high input connected to the high CAN bus connection and the first low power receiver low input connected to the low CAN bus connection;
a first wake up logic monitor having an input coupled to the first low power receiver output and having an output, a wake up indication being provided on the output when the first wake up logic monitor detects a wake up pattern on the CAN bus;

a second CAN bus transceiver having normal and standby modes, the second CAN bus transceiver including:
high and low CAN bus connections, the second CAN bus transceiver high CAN bus connection connected to the low CAN bus pin and the second CAN bus transceiver low CAN bus connection connected to the high CAN bus pin;
a second receiver hav

Assignees

• Texas Instruments Inc

Inventors

• Aarey Premanath Abhijeeth
• Hubbard Richard Edwin
• ROBERTSON Maxwell Guy
• Gupta Lokesh Kumar
• Wentroble Mark Edward
• Sperlich Roland
• Radic Dejan

Classifications

• H04L12/40176

  involving redundancy (error detection or correction of the data by redundancy in hardware using active fault-masking in interconnections G06F11/2002; error detection or correction of the data by redundancy in hardware using active fault-masking in storage systems using spares or by reconfiguring G06F11/2053) · CPC title

• H04L12/40013

  Details regarding a bus controller · CPC title

• H04L2012/40215

  Controller Area Network CAN · CPC title

• H04L12/40032 Primary

  Details regarding a bus interface enhancer · CPC title

• H04L12/40039

  Details regarding the setting of the power status of a node according to activity on the bus · CPC title