Capacitance Multiplier for Decoupling Capacitor
US-2023421136-A1 · Dec 28, 2023 · US
Grounded capacitance multipliers with electronic tuning possibility using single current feedback amplifier
US2018351536A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018351536-A1 |
| Application number | US-201715609034-A |
| Country | US |
| Kind code | A1 |
| Filing date | May 31, 2017 |
| Priority date | May 31, 2017 |
| Publication date | Dec 6, 2018 |
| Grant date | — |
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- Title
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Abstract
Official abstract text for this publication.
The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplier has less parasitic components, occupies a smaller chip area with higher simulated capacitance value.
First claim
Opening claim text (preview).
What is claimed is: 1 . A capacitance multiplier circuit, comprising: a current feedback operational amplifier having an x-terminal, a y-terminal, a z-terminal and a w-terminal, wherein a plus type current conveyor within the current feedback operational amplifier is provided; a capacitor having a first end of the capacitor connected to the x-terminal of the current feedback operational amplifier and a second end of the capacitor connected to an input node; a first resistor having a first end of the first resistor connected to the z-terminal of the current feedback operational amplifier and a second end of the first resistor connected to the second end of the capacitor; and a second resistor having a first end of the second resistor connected to the w-terminal of the current feedback operational amplifier and a second end of the second resistor connected to the second end of the first resistor. 2 . (canceled) 3 . (canceled) 4 . The capacitance multiplier circuit according to claim 1 , wherein at least one of the first resistor or the second resistor is constructed as voltage controlled resistor. 5 . The capacitance multiplier circuit according to claim 1 , wherein at least one of the first resistor or the second resistor is constructed as current controlled resistor. 6 . (canceled) 7 . (canceled) 8 . A capacitance multiplier circuit, comprising: a current feedback operational amplifier having an x-terminal, a y-terminal, a z-terminal and a w-terminal, wherein a negative type current conveyor within the current feedback operational amplifier is provided; a capacitor having a first end of the capacitor connected to the x-terminal of the current feedback operational amplifier and a second end of the capacitor connected to an input node; a first resistor having a first end of the first resistor connected to the z-terminal of the current feedback operational amplifier and a second end of the first resistor connected to the second end of the capacitor; and a second resistor having a first end of the second resistor connected to the w-terminal of the current feedback operational amplifier and a second end of the second resistor connected to the second end of the first resistor. 9 . The capacitance multiplier circuit according to claim 8 , wherein at least one of the first resistor or the second resistor is constructed as voltage controlled resistor. 10 . The capacitance multiplier circuit according to claim 8 , wherein at least one of the first resistor or the second resistor is constructed as current controlled resistor.
Assignees
Inventors
Classifications
Resistor · CPC title
using current feedback operational amplifiers · CPC title
- H03H11/483Primary
Simulating capacitance multipliers · CPC title
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Frequently asked questions
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- What does patent US2018351536A1 cover?
- The present invention relates to a capacitance multiplier topology suitable for both positive and negative capacitance multiplication having a minimum configuration consisting of a current feedback amplifier (CFOA), two resistors and a reference capacitor, with each C-multiplier having a respective capacitance amplification constant k which is externally adjustable. Such a capacitance multiplie…
- Who is the assignee on this patent?
- Univ Yeditepe
- What technology area does this patent fall under?
- Primary CPC classification H03H11/483. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Dec 06 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).