Data Driver and Display Apparatus Including the Same

Patent metadata

Field	Value
Publication number	US-2018342210-A1
Application number	US-201815915582-A
Country	US
Kind code	A1
Filing date	Mar 8, 2018
Priority date	May 26, 2017
Publication date	Nov 29, 2018
Grant date	—

Abstract

A voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups including a plurality of reference voltages, and a decoder having an output node configured to output one of the plurality of reference voltages is disclosed. The decoder includes switch blocks that correspond to the plurality of voltage groups. Each of the switch blocks includes transistors that are turned on or off by or in response to a control signal, and each transistor in one of the switch blocks has a channel width different from a channel width of each transistor in another one of the switch blocks.

First claim

What is claimed is:

1 . A digital-to-analog converter, comprising:
a voltage generator configured to generate a plurality of voltage groups, each of the plurality of voltage groups having a plurality of reference voltages; and a decoder having an output node configured to output one of the plurality of reference voltages from any of the plurality of voltage groups, wherein the decoder includes switch blocks that correspond to the plurality of voltage groups, each of the switch blocks includes transistors that are turned on or off by or in response to a control signal, and each transistor in one of the switch blocks has a channel width different from a channel width of each transistor in another one of the switch blocks.

2 . The digital-to-analog converter according to claim 1 , wherein the decoder further comprises connection nodes between the switch blocks and the output node, and the connection nodes have different widths.

3 . The digital-to-analog converter according to claim 1 , wherein the decoder further comprises first to (m−1)-th connection transistors between a first connection node and an m-th (m being a natural number greater than 1) connection node,
the first connection node is directly connected to a first transistor in a first one of the switch blocks and to a second transistor in a second one of the switch blocks, and
the m-th connection node is directly connected to two neighboring (m−1)-th connection transistors.

4 . The digital-to-analog converter according to claim 3 , wherein each of the (m−1)-th connection transistors is between the (m−1)-th connection node and the m-th connection node.

5 . The digital-to-analog converter according to claim 4 , wherein a transistor in one of the switch blocks has a size greater than that of a transistor in another one of the switch blocks, and
the reference voltages corresponding to the one of the switch blocks are higher than the reference voltages corresponding to the other one of the switch blocks.

6 . The digital-to-analog converter according to claim 4 , wherein the transistor in the one of the switch blocks has a breakdown voltage that is higher than that of the transistor in the other one of the switch blocks.

7 . The digital-to-analog converter according to claim 4 , wherein the (m−1)-th connection transistors have different channel widths.

8 . The digital-to-analog converter according to claim 7 , wherein one of the (m−1)-th connection transistors has a size that is greater than a size of another one of the (m−1)-th connection transistors, and
a voltage to the (m−1)-th connection node to which one end of the one (m−1)-th connection transistor is connected is higher than a voltage to the (m−1)-th connection node to which one end of the other (m−1)-th connection transistor is connected.

9 . The digital-to-analog converter according to claim 4 , wherein a breakdown voltage of one of the (m−1)-th connection transistors is different from that of another one of the (m−1)-th connection transistors.

10 . The digital-to-analog converter according to claim 9 , wherein the breakdown voltage of the one of the (m−1)-th connection transistors is higher than that of the other one of the (m−1)-th connection transistors, and
a voltage to the (m−1)-th connection node to which one end of the one (m−1)-th connection transistor is connected is higher than a voltage to the (m−1)-th connection node to which one end of the other (m−1)-th connection transistor is connected.

11 . The digital-to-analog converter according to claim 4 , wherein one of the (m−1)-th connection transistors has a same size as a size of the first transistor of the first switch block, and
the first switch block receives reference voltages equal to or higher than a voltage of an (m−1)-th connection node to which one end of the one (m−1)-th connection transistor is connected.

12 . The digital-to-analog converter according to claim 11 , wherein breakdown voltages of transistors of each switch block are equal to or higher than a maximum reference voltage of the reference voltages corresponding to said switch block.

13 . The digital-to-analog converter according to claim 4 , wherein the voltage generator includes reference voltage output nodes configured to output the plurality of reference voltages, and
transistors of the switch blocks are in a binary tree structure between the reference voltage output nodes and the first connection node.

14 . The digital-to-analog converter according to claim 13 , wherein the first to (m−1)-th connection transistors are in a binary tree structure between the first to m-th connection nodes.

15 . The digital-to-analog converter according to claim 14 , wherein the m-th connection node comprises the output node of the decoder.

16 . The digital-to-analog converter according to claim 13 , wherein the voltage generator includes a resistor string having serially connected resistors, and
the reference voltage output nodes include a connection node of two neighboring resistors of the serially connected resistors.

17 . The digital-to-analog converter according to claim 4 , wherein the channel widths of the (m−1)-th connection transistors are different from those of (m−2)-th connection transistors.

18 . The digital-to-analog converter according to claim 17 , wherein the channel width of one of the (m−1)-th connection transistors has a value between the channel widths of two (m−2)-th connection transistors directly connected to an (m−1)-th connection node to which the one (m−1)-th connection transistor is connected.

19 . A data driver comprising:
a data storage unit configured to store a data signal; a level shifting block configured to shift a voltage level of the data signal and output a level-shifted data signal; and the analog-to-digital converter according to claim 1 , configured to output one of the plurality of reference voltages based on or in response to the level-shifted data signal.

20 . A display apparatus comprising:
a display panel including gate lines in rows, data lines in columns and intersecting the gate lines in a matrix, and pixels each connected to respective gate lines and intersecting data lines; a gate driver configured to drive the gate lines; and the data driver according to claim 19 , configured to drive the data lines.

Assignees

• Db Hitek Co Ltd

Inventors

• Choi Kee Joon
• Kim Hae Taek
• Lee Sang Gi

Classifications

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• H03M1/76

  using switching tree · CPC title

• G09G3/3696

  Generation of voltages supplied to electrode drivers · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title