Method for assigning an input channel as well as signal analyzer

Patent metadata

Field	Value
Publication number	US-2018337754-A1
Application number	US-201715599077-A
Country	US
Kind code	A1
Filing date	May 18, 2017
Priority date	May 18, 2017
Publication date	Nov 22, 2018
Grant date	—

Abstract

A method for assigning an input channel of a signal analyzer to a signal decoder has the steps of analyzing a digital representation of a signal received by an input channel and generating a characteristic signal parameter of the signal. The parameter is compared to expected values and the corresponding input channel is assigned to the signal decoder according to the result of the comparison. Further, a signal analyzer for measuring a bus signal is shown.

First claim

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:

1 . A method for assigning an input channel of a plurality of input channels of a signal analyzer to a signal decoder of said signal analyzer, comprising the following steps:
choosing a first input channel of said plurality of input channels; analyzing a digital representation of a first signal received by said first input channel by generating at least one characteristic signal parameter of said first signal; performing a check whether said at least one characteristic signal parameter corresponds to an expected value; and assigning said first input channel to said signal decoder according to the result of said check.

2 . The method according to claim 1 , wherein said first input channel is assigned as one of a data input and a clock signal input of said signal decoder.

3 . The method according to claim 1 , wherein said input channel is assigned to said signal decoder using a multiplexer.

4 . The method according to claim 3 , wherein said digital representation of said signal is temporarily stored in a memory unit provided between said signal decoder and said multiplexer.

5 . The method according to claim 1 , wherein said digital representation of said first signal is analyzed using said signal decoder.

6 . The method according to claim 1 , wherein said check is performed by a control unit of said signal analyzer, said control unit receiving said at least one characteristic signal parameter.

7 . The method according to claim 1 , wherein a second input channel of said plurality of input channels is chosen and said analyzing, said performing, and said assigning are repeated for said second input channel.

8 . The method according to claim 1 , wherein said expected value is characteristic of at least one of a data signal, a clock signal, a bus signal, a number of bits, events, and a specific bus type.

9 . The method according to claim 1 , wherein said at least one characteristic signal parameter is at least one of a frequency of said signal, a maximum amplitude of said signal, a minimum amplitude of said signal, a decoded bus signal, and a bus load.

10 . The method according to claim 1 , wherein said signal analyzer is at least one of an oscilloscope and a logic analyzer.

11 . The method according to claim 1 , wherein said signal decoder outputs a decoded signal, said decoded signal is displayed using a display unit of said signal analyzer.

12 . The method according to claim 11 , wherein said decoded signal passes a memory unit provided between said signal decoder and said display unit.

13 . A signal analyzer for measuring a bus signal, comprising:
a plurality of input channels, a signal decoder, a multiplexer connecting said input channel to said signal decoder, and a control unit, said signal decoder being configured to receive a digital representation of a first signal received by a first input channel of said plurality of input channels and said signal decoder being configured to generate at least one characteristic signal parameter of said first signal, said control unit being configured to receive said characteristic signal parameter from said signal decoder and to perform a check whether said at least one characteristic signal parameter corresponds to an expected value, and said control unit being configured to control said multiplexer to assign said first input channel to said signal decoder according to the result of said check.

14 . The signal analyzer according to claim 13 , wherein said signal analyzer comprises at least one analog-to-digital-converter associated with said first input channel for generating said digital representation of said first signal.

15 . The signal analyzer according to claim 13 , wherein said first input channel is assigned as one of a data input and a clock signal channel of said signal decoder.

16 . The signal analyzer according to claim 13 , wherein said expected value is characteristic of at least one of a data signal, a clock signal, a bus signal, a number of bits, events, and a specific bus type.

17 . The signal analyzer according to claim 13 , wherein said at least one characteristic signal parameter is at least one of a frequency of said signal, a maximum amplitude of said signal, a minimum amplitude of said signal, a decoded bus signal, and a bus load.

18 . The signal analyzer according to claim 13 , wherein said signal analyzer is at least one of an oscilloscope and a logic analyzer.

19 . The signal analyzer according to claim 13 , wherein said signal analyzer comprises a display unit receiving and displaying a decoded signal from said signal decoder.

20 . The signal analyzer according to claim 13 , wherein at least one memory unit is provided in the signal path between at least one of said signal decoder and said multiplexer as well as between said signal decoder and said display unit.

Assignees

• Rohde & Schwarz

Inventors

• Diegmann Philip
• Pfefferkorn Moritz

Classifications

• H04W24/00

  Supervisory, monitoring or testing arrangements · CPC title

• H04L2001/0094

  Bus · CPC title

• H04W72/02

  Selection of wireless resources by user or terminal · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L5/0058

  Allocation criteria · CPC title