Forming an isolation barrier in an isolator

Patent metadata

Field	Value
Publication number	US-2018337084-A1
Application number	US-201715600664-A
Country	US
Kind code	A1
Filing date	May 19, 2017
Priority date	May 19, 2017
Publication date	Nov 22, 2018
Grant date	—

Abstract

Integrated digital isolators comprise a first transformer coil or capacitor plate mounted on an integrated circuit substrate, and separated from a second transformer coil or capacitor plate via an electrically insulating isolation layer. The electrical isolation that is achieved is dependent upon the material and thickness of the isolation layer. In order to reduce the amount of time required for fabrication while still allowing thick isolation layers to be deployed, in examples of the disclosure pre-formed sheets or tapes of dielectric material are applied to the substrate over the first transformer coil or capacitive plate, for example by being rolled onto the substrate using a heated roller. Such a technique results in a thick isolation layer that is formed using a simple process and much more quickly and reliably than conventional spin-coating or deposition techniques.

First claim

1 . A method of forming a dielectric insulation layer in an integrated isolator circuit, comprising:
receiving a partially formed integrated isolator circuit structure having a first electrode set formed on a substrate wafer; applying a pre-formed dielectric sheet or tape over the partially formed integrated isolator circuit structure; and depositing and patterning a metallization layer to form a second electrode set on the applied pre-formed dielectric sheet or tape.

2 . A method according to claim 1 , wherein applying the pre-formed dielectric sheet or tape comprises rolling the pre-formed dielectric sheet or tape onto the partially formed integrated isolator structure from one side of the structure to the other.

3 . A method according to claim 2 , wherein rolling the pre-formed dielectric sheet or tape comprises rolling the pre-formed dielectric sheet or tape with the aid of a roller tool.

4 . A method according to claim 1 , wherein the pre-formed dielectric sheet or tape is a polymer material.

5 . A method according to claim 4 , wherein the pre-formed dielectric sheet or tape is a polyimide sheet or tape.

6 . A method according to claim 5 , wherein the polyimide sheet or tape is between 40 and 80 microns in thickness.

7 . A method according to claim 1 , wherein applying the pre-formed dielectric sheet or tape comprises applying the pre-formed dielectric sheet or tape onto a surface of the partially formed integrated isolator structure substantially simultaneously across the surface, the application being performed in a vacuum environment sufficient to prevent the formation of gas bubbles beneath the sheet or tape as it is applied.

8 . A method according to claim 1 , wherein the pre-formed dielectric sheet or tape is a dry film resist.

9 . A method according to claim 1 , wherein the pre-formed dielectric sheet or tape is a laminating sheet, and wherein the method further comprises dicing the substrate wafer into individual integrated isolator circuit structures after the application of the pre-formed dielectric sheet or tape and before the depositing and patterning of the metallization layer.

10 . A method according to claim 1 , wherein the integrated isolator circuit is a digital isolator circuit.

11 . A method of fabricating an integrated digital isolator circuit, comprising:
forming a first electrode set on an integrated circuit wafer substrate; rolling a pre-formed sheet or tape of dielectric material having a predetermined thickness to give a predetermined electrical isolation property over the first electrode set; and depositing and patterning a metallization layer to form a second electrode set on the pre-formed sheet or tape of dielectric material.

12 . A method according to claim 11 , further comprising forming a first passivation layer over the first electrode set prior to the rolling of the pre-formed sheet or tape, the first passivation layer having vias formed therein electrically contacting at least part of the first electrode set.

13 . A method according to claim 12 , further comprising forming a second passivation layer over the second electrode set, the second passivation layer having vias formed therein electrically contacting at least part of the second electrode set.

14 . A method according to claim 11 , wherein the first and second electrode sets comprise respective conducting coil structures forming a transformer.

15 . A method according to claim 11 , wherein the first and second electrode sets comprise respective conducting capacitor plates.

16 . A method according to claim 11 , wherein the pre-formed sheet or tape comprises polyimide or dry-film resist.

17 .- 20 . (canceled)

21 . A method of fabricating an integrated digital isolator circuit, comprising:
applying a dielectric sheet or tape having a predetermined thickness over a first electrode formed on a wafer substrate; and depositing and patterning a metallization layer to form a second electrode on the dielectric sheet or tape.

22 . The method of claim 21 , wherein the dielectric sheet or tape has a substantially uniform thickness.

23 . The method of claim 21 , wherein the applying a dielectric sheet or tape is performed in a vacuum environment that prevents formation of air or gas bubbles beneath the dielectric sheet or tape.

24 . The method of claim 21 , wherein the dielectric sheet or tape applied over the first electrode is substantially devoid of wrinkles or folds.

Assignees

• Analog Devices Global

Inventors

• Blennerhassett Alan John
• Stenson Bernard Patrick

Classifications

• H10W44/601

  Capacitive arrangements (H10W44/20 takes precedence) · CPC title

• H10W20/497 Primary

  Inductive arrangements or effects of, or between, wiring layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/01

  Manufacture or treatment · CPC title