Minimum pulse-width assurance

Patent metadata

Field	Value
Publication number	US-2018331677-A1
Application number	US-201816042103-A
Country	US
Kind code	A1
Filing date	Jul 23, 2018
Priority date	Dec 22, 2016
Publication date	Nov 15, 2018
Grant date	—

Abstract

Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW circuit. A first input of the second logic circuit is communicatively coupled to an output of the first logic circuit. The MPW circuit also comprises a MPW filter circuit communicatively coupled to an output of the second logic circuit, a one-shot circuit communicatively coupled to an output of the minimum pulse-width filter circuit and located on a first feedback path, and another one-shot circuit communicatively coupled to the output of the minimum pulse-width filter circuit and located on a second feedback path. A second input of the first logic circuit is on the first feedback path. A second input of the second logic circuit is on the second feedback path.

First claim

What is claimed is:

1 . A method for assuring a minimum pulse-width using a minimum pulse-width assurance circuit, the method comprising:
receiving a first signal at a first input of a first logic circuit, wherein the first input of the first logic circuit is coupled to an input of the minimum pulse-width assurance circuit; receiving, at a second input of the first logic circuit, a second signal from a first one-shot circuit; receiving, at a first input of a second logic circuit, a third signal from the first logic circuit, wherein the third signal is based on the first signal and the second signal; receiving, at a second input of the second logic circuit, a fourth signal from a second one-shot circuit; receiving, at an input of a minimum pulse-width filter circuit, a fifth signal from the second logic circuit, wherein the fifth signal is based on the third signal and the fourth signal, and wherein an output of the minimum pulse-width filter circuit is communicatively coupled to an output of the minimum pulse-width assurance circuit; receiving, at an input of the first one-shot circuit and at an input of the second one-shot circuit, a sixth signal from the minimum pulse-width filter circuit, wherein the sixth signal is generated based on a pulse width of the fifth signal; receiving, at the second input of the first logic circuit, a seventh signal from the first one-shot circuit, wherein the seventh signal is based on a signal transition of the sixth signal; and receiving, at the second input of the second logic circuit, an eighth signal from the second one-shot circuit, wherein the eighth signal is based on the signal transition of the sixth signal.

2 . The method of claim 1 , wherein:
the third signal is based on a logic operation performed by the first logic circuit on the first signal and the second signal.

3 . The method of claim 1 , wherein:
the fifth signal is based on a logic operation performed by the second logic circuit on the third signal and the fourth signal.

4 . The method of claim 1 , wherein:
the sixth signal comprises no pulse if the pulse width of the fifth signal is less than a width of a maximum rejectable pulse; and the sixth signal comprises a pulse if the pulse width of the fifth signal is greater than a width of a minimum allowable pulse.

5 . The method of claim 1 , wherein the minimum pulse-width filter circuit comprises:
a low-pass filter communicatively coupled to an output of the second logic circuit; and a Schmitt trigger circuit coupled to an output of the low-pass filter; wherein an output of the Schmitt trigger circuit is the output of the minimum pulse-width filter circuit.

6 . The method of claim 5 , wherein the low-pass filter comprises:
a filter resistor that couples the output of the second logic circuit to an input of the Schmitt trigger circuit; and a filter capacitor that couples the input of the Schmitt trigger circuit to a DC bias voltage node.

7 . The method of claim 6 , wherein:
the filter resistor and the filter capacitor smooth a pulse edge of a minimum allowable pulse provided to the low-pass filter; and the Schmitt trigger circuit sharpens the pulse edge of the minimum allowable pulse.

8 . The method of claim 6 , wherein:
the filter resistor and the filter capacitor smooth a pulse edge of a maximum rejectable pulse provided to the low-pass filter; and the Schmitt trigger circuit is not-responsive to the pulse edge of the maximum rejectable pulse.

9 . The method of claim 1 , wherein the first one-shot circuit and the second one-shot circuit each individually comprises:
a diode connected to the output of the minimum pulse-width filter circuit and a one-shot circuit node; a resistor connected to the output of the minimum pulse-width filter circuit and the one-shot circuit node; a capacitor that couples the one-shot circuit node to a DC bias voltage node; and a third logic circuit communicatively coupled to the one-shot circuit node; wherein an output of the third logic circuit of the first one-shot circuit is an output of the first one-shot circuit; and wherein an output of the third logic circuit of the second one-shot circuit is an output of the second one-shot circuit.

10 . The method of claim 9 , wherein:
the first logic circuit is an AND gate; the second logic circuit is an OR gate; the third logic circuit of the first one-shot circuit is an OR gate; and the third logic circuit of the second one-shot circuit is an AND gate.

11 . The method of claim 1 , wherein:
the first one-shot circuit extends a low pulse of the sixth signal to a first minimum width; and the second one-shot circuit extends a high pulse of the sixth signal to a second minimum width.

12 . The method of claim 1 , wherein the minimum pulse-width assurance circuit communicatively couples a pulse-width modulator comparator to a gate driver in a power converter.

13 . The method of claim 12 , wherein the minimum pulse-width assurance circuit further comprises:
a buffer connected to the output of the minimum pulse-width filter circuit; and a third input of the first logic circuit communicatively coupled to a pulse-width modulator blank signal source; wherein the input of the minimum pulse-width assurance circuit is connected to the pulse-width modulator comparator; and wherein an output of the buffer is communicatively coupled to the gate driver.

14 . The method of claim 1 , wherein:
the minimum pulse-width assurance circuit is absent of digital latches; and the first one-shot circuit and the second one-shot circuit do not use a clock signal.

15 . The method of claim 1 , wherein:
the seventh signal comprises a first pulse generated by the first one-shot circuit in response to a high-to-low signal transition of a low pulse of the sixth signal; the eighth signal comprises a second pulse generated by the second one-shot circuit in response to a low-to-high signal transition of a high pulse of the sixth signal; the first one-shot circuit extends the low pulse of the sixth signal to a first minimum width; and the second one-shot circuit extends the high pulse of the sixth signal to a second minimum width.

16 . The method of claim 1 , wherein:
the seventh signal comprises a first pulse generated by the first one-shot circuit in response to a low-to-high signal transition of a high pulse of the sixth signal; the eighth signal comprises a second pulse generated by the second one-shot circuit in response to a high-to-low signal transition of a low pulse of the sixth signal; the first one-shot circuit extends the high pulse of the sixth signal to a first minimum width; and the second one-shot circuit extends the low pulse of the sixth signal to a second minimum width.

Assignees

• Silanna Asia Pte Ltd

Inventors

• Arbetter Barry S

Classifications

• H02M3/158

  including plural semiconductor devices as final control devices for a single load · CPC title

• H03K5/1252

  Suppression or limitation of noise or interference (specially adapted for transmission systems H04B15/00, H04L25/08) · CPC title

• H03K5/156

  Arrangements in which a continuous pulse train is transformed into a train having a desired pattern · CPC title

• H02M1/32

  Means for protecting converters other than automatic disconnection · CPC title

• H03K5/04

  by increasing duration; by decreasing duration · CPC title