Delay circuitry to hold up power to a mass storage device and method therefor

Patent metadata

Field	Value
Publication number	US-2018322011-A1
Application number	US-201815971712-A
Country	US
Kind code	A1
Filing date	May 4, 2018
Priority date	May 4, 2017
Publication date	Nov 8, 2018
Grant date	—

Abstract

A delay circuitry is configured to hold up power to a mass storage device after a power fault disables communication of the mass storage device with the host computer. The time delay is sufficient to allow saving of in-flight data from the storage device's volatile cache to the non-volatile media (of the storage device) and to update a metadata table in the non-volatile media.

First claim

1 . A computer device, comprising:
an enclosure having one or more host computers powered by a power supply; a plurality of non-volatile memory mass storage devices having a volatile memory cache and a non-volatile memory data carrier; a plurality of interposer boards, the one or more host computers communicatively coupled to the plurality of non-volatile memory mass storage devices by the plurality of interposer boards; where at least one of the host computers in the one or more host devices is configured to exchange data and control signals with selected non-volatile memory devices in the plurality of non-volatile memory mass storage devices; and where each of the interposer boards in the plurality of interposer boards comprises:
a first e-fuse to gate power to a logic circuit on the at least one interposer board along a data path to a first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices;
a second e-fuse to gate power to the first non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices, wherein the first and the second e-fuses are logically connected to fault the second e-fuse when a fault condition occurs on the first e-fuse; and
a delay circuit, coupled between the first e-fuse and the second e-fuse, configured to delay the fault of the second e-fuse after the fault of the first e-fuse.

2 . The computer device of claim 1 , further comprising a midplane coupled between the one or more host devices and the plurality of interposer boards.

3 . The computer device of claim 1 , wherein the fault of the second e-fuse causes power to be turned Off to the first non-volatile memory mass storage device after a time delay caused by the delay circuit, the time delay relative to the fault of the first e-fuse.

4 . The computer device of claim 3 , wherein the time delay provides sufficient time for data to be copied from the volatile cache memory in the first non-volatile memory mass storage device to the non-volatile memory data carrier.

5 . The computer device of claim 1 , further comprising:
a multiplexing control logic circuit on the interposer boards, the multiplexing logic configured to select a non-volatile mass storage device in the plurality of non-volatile memory devices by the one or more host computers, where a power converter powers the multiplexing control logic circuit.

6 . The computer device of claim 5 , wherein the delay circuit comprises:
an array of capacitors having one or more capacitors; a supply voltage adapted to charge the one or more capacitors in the array of capacitors; a first metal-oxide-semiconductor field-effect transistor (MOSFTET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance state to ground, the high resistance state of the first MOSFET preventing the supply voltage to the array of capacitors from draining to ground and causing charging of the array of capacitors; and a second MOSFET coupled to the array of capacitors, wherein when a charge of the one or more capacitors in the array of capacitors exceeds a gate threshold voltage of the second MOSFET, the second MOSFET switches from a high resistance state to a low resistance state, and the low resistance state of the second MOSFET causes the second e-fuse to turn Off power to the first non-volatile memory mass storage device.

7 . The computer device of claim 6 , further comprising a first resistor coupled between the supply voltage and the array of capacitors for limiting an inrush current; and wherein a second resistor coupled between the array of capacitors and the first MOSFET for limiting a drain of the first MOSFET to ground.

8 . The computer device of claim 6 , wherein the second e-fuse includes a sense resistor for sensing an over current condition on the first non-volatile memory mass storage device.

9 . The computer device of claim 1 , wherein the non-volatile memory mass storage devices include non-volatile memory express (NVMe) devices and/or peripheral component interconnect express (PCIe) devices.

10 . The computer device of claim 6 , wherein the supply voltage is 12 volts.

11 . The computer device of claim 6 , wherein the power converter provides a voltage of 3.3 volts or 1.8 volts.

12 . A method for power fail protection of a plurality of non-volatile memory devices in a computer device having an enclosure, a power supply unit, one or more host computers, a midplane and interposer boards to connect non-volatile memory mass storage devices with the one or more host computers, the method comprising:
configuring a host computer to exchange data and control signals with a selected non-volatile memory mass storage device in the plurality of non-volatile memory mass storage devices; providing power from a midplane supply voltage source to a multiplexing logic circuit along a data/signal path to the plurality of non-volatile memory mass storage device, and from the midplane supply voltage source to the plurality of non-volatile memory mass storage device; and automatically triggering a power shutoff, after a predictable time delay, of the plurality of non-volatile memory mass storage devices upon detecting a power fault condition along the data/signal path.

13 . The method of claim 12 , wherein the time delay is effectuated by delay circuit including an array of capacitors, the array of capacitors being charged by the midplane supply voltage source.

14 . The method of claim 12 , wherein the time delay provides sufficient time for data to be copied from a cache memory in the first non-volatile memory mass storage device to the non-volatile memory data carriers.

15 . A circuit, comprising:
a non-volatile memory mass storage device having a volatile memory device and non-volatile data carrier, the volatile memory device configured to cache data prior to storing the data on non-volatile memory data carriers in the plurality of non-volatile memory mass storage devices; a power supply providing power, along a first power path, to a logic circuit along a data path to the storage device, and along a second power path to the storage device; a power fault detection circuit adapted to remove power from the second power path when a power fault is detected along the first power path; and a delay circuit configured to delay shutting off the non-volatile memory mass storage device after detection of the power fault along the first power path, the delay circuit providing time for the data to be copied from the volatile memory device to the non-volatile memory data carriers.

16 . The circuit of claim 15 , wherein the delay circuit comprises:
an array of capacitors having one or more capacitors; a supply voltage adapted to charge the one or more capacitors in the array of capacitors; a first metal-oxide-semiconductor field-effect transistor (MOSFTET) connected to the array of capacitors, wherein when in a non-fault condition, the first MOSFET is in a low-resistance state to connect the supply voltage to the one or more capacitors in the array of capacitors to a ground; and when a fault condition from the power converter powering the multiplexing logic circuit and connected to a gate of the first MOSFET switches the first MOSFET to a high resistance

Assignees

• Sanmina Corp

Inventors

• Batcheller Paul
• Bowman Matthew
• Doblar Drew G
• Schuette Franz Michael

Classifications

• G06F11/1441

  Resetting or repowering · CPC title

• H05K1/0293

  Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches · CPC title

• G06F1/30

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• H03K2005/00195

  using FET's · CPC title

• H03K2005/00078

  Fixed delay · CPC title