Storing Address of Spare in Failed Memory Location

Patent metadata

Field	Value
Publication number	US-2018314592-A1
Application number	US-201816029829-A
Country	US
Kind code	A1
Filing date	Jul 9, 2018
Priority date	Sep 29, 2015
Publication date	Nov 1, 2018
Grant date	—

Abstract

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

First claim

What is claimed is:

1 . A system comprising:
a memory; and an integrated circuit (IC) coupled to the memory, wherein: the memory is divided into a first partition and a second partition; the first partition is divided into a plurality of entries, the entries storing a status indication, a block of data, and error correction code (ECC) data; during a write to a first entry of the plurality of entries by the IC, the status indication in the first entry is checked to determine whether or not the first entry has previously failed; responsive to the status indication indicating that the first entry has previously failed, the IC is configured to use at least a portion of the block of data in the first entry as an address to a second entry in the second partition; attempting to write to the second entry, wherein the second entry also includes the status indication; during the write to the second entry, the status indication in the second entry is checked to determine whether or not the second entry has previously failed; responsive to the status indication indicating that the second entry has previously failed, the IC is configured to use at least a portion of the block of data in the second entry as a second address to a third entry in the second partition; attempting to write to the third entry.

2 . The system as recited in claim 1 wherein:
a result of the write is checked and, if a failure is detected, the IC is configured to select an unused entry from the second partition and to write the block of data and ECC data to the unused entry; and
the IC is configured to write the status indication in the first entry to indicate failure in response to detecting the failure.

3 . The system as recited in claim 1 wherein the IC is configured to write, to the first entry along with the status indication, N copies of: an address of the spare entry and ECC covering the address, wherein N is an integer greater than one.

4 . A system comprising:
a memory including a first plurality of entries and a second plurality of entries, wherein a memory address space of the system is mapped to the first plurality of entries, and wherein a given entry of the first plurality of entries is configured to store a status indication that indicates whether or not the given entry has been detected as failed, a block of data, and error correction code (ECC) data covering the block of data, and the status indication comprises a plurality of bits that redundantly encode the indication of whether or not the given entry has been detected as failed; and an integrated circuit coupled to the memory, wherein the integrated circuit is configured to access a first entry of the first plurality of entries responsive to a first memory operation, and wherein the integrated circuit is configured to check the status indication from the first entry, and, responsive to the status indication indicating failed, the integrated circuit is configured to access a second entry of the second plurality of entries that was allocated when the failure of the first entry was detected.

5 . The system as recited in claim 4 wherein each bit of the status indication is set to indicate failed, and wherein any set bit in the status indication being set is interpreted as a failed status.

6 . The system as recited in claim 4 wherein the first entry further includes an indication of the second entry when the status indication indicates failed.

7 . The system as recited in claim 6 wherein the indication of the second entry comprises an address of the second entry and second ECC data covering the address, wherein a first ratio of a first number of bits in the second ECC data to a second number of bits in the address is greater than a second ratio of a third number of bits in the ECC data that covers the block of data to a fourth number of bits in the block of data.

8 . The system as recited in claim 7 wherein the indication of the second entry comprises N instances of both the address of the second entry and the second ECC data.

9 . The system as recited in claim 4 wherein, responsive to a second status indication in the second entry indicating failed, the integrated circuit is configured to access a third entry of the second plurality of entries, wherein the third entry was allocated when failure of the second entry was detected.

10 . The system as recited in claim 4 wherein, in addition to memory accesses in response to memory operations, the integrated circuit is configured to perform a periodic write that includes selecting an entry in the memory, reading a content of the selected entry, correcting any detected errors in the content, and writing the corrected data back to the selected entry.

11 . The system as recited in claim 4 wherein, if the first memory operation is a read, the integrated circuit is configured to read the block of data from the second entry in response to the first entry having a status indication indicating failed, and wherein the integrated circuit is configured to check the ECC on the block of data and to forward the block of data to the source of the first memory operation if no error is detected.

12 . The system as recited in claim 11 wherein the integrated circuit is configured to correct the block of data if correctable errors are detected and forward the corrected data to the source.

13 . The system as recited in claim 12 wherein the integrated circuit is configured to write back the corrected data to the second entry responsive to correcting the correctable errors in the block of data.

14 . The system as recited in claim 4 wherein, if the first memory operation is a write, the integrated circuit is configured to read a second status indication from the second entry responsive to the status indication in the first entry indicating failed and, if the second status indication does not indicate failed, the integrated circuit is configured to write data from the first memory operation to the second entry, read the data back from the second entry, and check the read back data for errors.

15 . The system as recited in claim 14 wherein, responsive to detecting a failure in the second entry via checking the read back data for errors, the integrated circuit is configured to allocate a third entry of the plurality of entries, write the data from the first memory operation to the third entry, and write a second status indication of the second entry to indicate failed.

16 . The system as recited in claim 14 wherein, responsive to detecting errors in the read back data but not a failure of the second entry, the integrated circuit is configured to write the corrected read back data to the second entry.

17 . The system as recited in claim 14 wherein, in addition to memory accesses in response to memory operations, the integrated circuit is configured to perform a periodic write that includes selecting an entry in the memory, reading a content of the selected entry, correcting any detected errors in the content, and writing the corrected data back to the selected entry, and wherein the integrated circuit is configured to select a neighboring entry to the second entry as the selected entry in response to performing the periodic write at a time that the first memory operation is being performed.

18 . The system as recited in claim 4 wherein the integrated circuit is configured to detect a failure in an entry of the memory responsive to detecting a number of bit errors in the block of data in the entry exceeding a threshold.

19 . The system as rec

Assignees

• Apple Inc

Inventors

• Gulati Manu
• Biswas Sukalpa
• Wilcox Jeffrey R
• Nemati Farid

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G06F2212/7207

  management of metadata or control data · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title

• G11C2029/0411

  Online error correction · CPC title