Semiconductor device and test method for semiconductor device

Patent metadata

Field	Value
Publication number	US-2018313894-A1
Application number	US-201815954665-A
Country	US
Kind code	A1
Filing date	Apr 17, 2018
Priority date	Apr 28, 2017
Publication date	Nov 1, 2018
Grant date	—

Abstract

A logic BIST circuits concurrently execute a first scan test for a scan chain as a target and a second scan test for a scan chain as a target, when they are set to an LBIST mode, and execute the first scan test without executing the second scan test, when they are set to a simultaneous test mode. Memory BIST circuits execute a test for memory circuits concurrently with the first scan test, when they are set to the simultaneous test mode. Logic BIST circuits complete a test with the LBIST mode, at a stage where the second scan test has completed.

First claim

What is claimed is:

1 . A semiconductor device configured with one semiconductor chip, comprising:
a memory circuit unit which includes a memory circuit and an interface for test for the memory circuit; a logic circuit which performs a predetermined logical operation; a memory BIST (Built In Self Test) circuit which tests the memory circuit; and a logic BIST circuit which tests the logic circuit and the memory BIST circuit, wherein at least a part of the logic circuit is incorporated in a first scan chain, wherein the memory BIST circuit is incorporated in a second scan chain, wherein the logic BIST circuit concurrently executes a first scan test for the first scan chain as a target and a second scan test for the second scan chain as a target, when it is set to a first test mode, and executes the first scan test without executing the second scan test, when it is set to a second test mode, wherein the memory BIST circuit executes a test for the memory circuit concurrently with the first scan test, when it is set to the second test mode, wherein a time for executing the first scan test is longer than a time for executing the second scan test, and wherein the logic BIST circuit completes a test with the first test mode, at a stage where the second scan test has been completed.

2 . The semiconductor device according to claim 1 , further comprising
a POST (Power On Self Test) circuit which sequentially sets the first test mode and the second test mode, in response to power supply of the semiconductor device.

3 . The semiconductor device according to claim 1 ,
wherein the logic circuit incorporated in the first scan chain includes a memory pre-stage logic circuit issuing an instruction for accessing to the memory circuit and a memory post-stage logic circuit to which read data from the memory circuit is input.

4 . The semiconductor device according to claim 3 ,
wherein the memory circuit unit includes
a scan flip flop circuit for bypass which has a function for bypassing an input and/or an output of the memory circuit, and selectively latches an input signal for the memory circuit or a scan-in signal, and
a path switch circuit which transmits an output signal of the scan flip flop circuit for bypass to the memory BIST circuit and the memory post-stage logic circuit, when it is set to the first test mode, transmits an output signal of the scan flip flop circuit for bypass to the memory post-stage logic circuit, when it is set to the second test mode, and transmits an output signal of the memory circuit to the memory BIST circuit,
wherein the scan-in signal of the scan flip flop circuit for bypass is an output signal of any scan flip flop circuit in the logic circuit incorporated in the first scan chain, and wherein the scan flip flop circuit for bypass fixedly latches the scan-in signal, when it is set to the second test mode.

5 . The semiconductor device according to claim 4 , further comprising:
a selection circuit which selects a signal from the memory pre-stage logic circuit or a signal from the memory BIST circuit, and outputs the selected signal to the memory circuit and the scan flip flop circuit for bypass.

6 . The semiconductor device according to claim 1 , further comprising:
a JTAG interface circuit which performs communication with an external device based on a JTAG standard, and a mode decoder which sets the second test mode, in response to an instruction from the external device through the JTAG interface circuit.

7 . A semiconductor device which is configured with one semiconductor chip, comprising:
a memory circuit unit which includes a memory circuit and an interface for test for the memory circuit; a logic circuit which includes a memory pre-stage logic circuit issuing an instruction for accessing to the memory circuit and a memory post-stage logic circuit to which read data from the memory circuit is input, and performs a predetermined logical operation; a memory BIST (Built In Self Test) circuit which tests the memory circuit; and a logic BIST circuit which tests the logic circuit and the memory BIST circuit, wherein the memory circuit includes:
a first scan flip flop circuit for bypass which has a function for bypassing an input and/or an output of the memory circuit, and selectively latches an input signal for the memory circuit or a scan-in signal, and
a path switch circuit which transmits an output signal of the first scan flip flop circuit for bypass to the memory BIST circuit and the memory post-stage logic circuit, when it is set to a first test mode, transmits an output signal of the first scan flip flop circuit for bypass to the memory post-stage logic circuit, when it is set to a second test mode, and transmits an output signal of the memory circuit to the memory BIST circuit.

8 . The semiconductor device according to claim 7 ,
wherein the path switch circuit includes
a first selection circuit which selects an output signal of the memory circuit or an output signal of the first scan flip flop circuit for bypass, and
a second selection circuit which selects an output signal of the first selection circuit or an output signal of the first scan flip flop circuit for bypass.

9 . The semiconductor device according to claim 8 ,
wherein the memory circuit, the first scan flip flop circuit for bypass, and the first selection circuit are configured with a hard macro.

10 . The semiconductor device according to claim 7 , further comprising:
a second scan flip flop circuit for bypass which selectively latches an input signal for the memory circuit or a scan-in signal as a same as a scan-in signal of the first scan flip flop circuit for bypass; a first selection circuit which selects an output signal of the memory circuit or an output signal of the first scan flip flop circuit for bypass; and a second selection circuit which selects an output signal of the first selection circuit or an output signal of the second scan flip flop circuit.

11 . The semiconductor device according to claim 7 ,
wherein the first scan flip flop circuit for bypass fixedly latches the scan-in signal, when it is set to the second test mode.

12 . A test method for a semiconductor device which is configured with one semiconductor chip, the semiconductor device comprising:
a memory circuit unit which includes a memory circuit and an interface for test for the memory circuit; a logic circuit which performs a predetermined logical operation; a memory BIST (Built In Self Test) circuit which tests the memory circuit; and a logic BIST circuit which tests the logic circuit and the memory BIST circuit, wherein at least a part of the logic circuit is incorporated in a first scan chain, wherein the memory BIST circuit is incorporated in a second scan chain, wherein the test method has
a first step, by the logic BIST circuit, of concurrently executing a first scan test for the first scan chain as a target and a second scan test for the second scan chain as a target, and
a second step, by the logic BIST circuit, of executing the first scan test without executing the second scan test, and, by the memory BIST circuit, of executing a test for the memory circuit concurrently with the first scan test,
wherein a time for executing the first scan test is longer than a time for executing the second scan test, and wherein the first step is completed at a stage where the second scan test is completed.

13 . The test method for the semiconductor device according to claim 12 ,
wherein the first step and the second step are performed in response to power supply of the semiconductor device.

Assignees

• Renesas Electronics Corp

Inventors

• Suzuki Iwao
• Kato Naoki

Classifications

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title

• G06F11/2284

  by power-on test, e.g. power-on self test [POST] · CPC title

• G11C29/38 Primary

  Response verification devices · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/318597

  JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32) · CPC title