Semiconductor device and method of manufacturing the semiconductor device

Patent metadata

Field	Value
Publication number	US-2018308957-A1
Application number	US-201815898201-A
Country	US
Kind code	A1
Filing date	Feb 15, 2018
Priority date	Apr 25, 2017
Publication date	Oct 25, 2018
Grant date	—

Abstract

An insulating film configuring an uppermost layer of a gate insulating film of a memory cell comprises a silicon oxide film and is a layer to which a metal or metal oxide is added. A formation step of the insulating film comprises the steps of: forming the silicon oxide film; and adding the metal or the metal oxide in an atomic or molecular state by a sputtering process onto the silicon oxide film. Oxide of the metal has a higher dielectric constant than silicon oxide, and the metal oxide has a higher dielectric constant than silicon oxide. A High-K added layer is thus used as the insulating film configuring the gate insulating film of the memory cell, thereby a high saturation level of a threshold voltage can be maintained while a drive voltage (applied voltage for erase or write) is reduced, leading to improvement in reliability of the memory cell.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a semiconductor substrate; and a nonvolatile memory cell disposed in a first region of the semiconductor substrate, wherein the nonvolatile memory cell comprises: a first gate electrode disposed over the semiconductor substrate; and a first insulating film that is formed between the first gate electrode and the semiconductor substrate, and internally has a charge storage part, wherein the first insulating film comprises: a first film comprising a silicon oxide film formed over the semiconductor substrate; a second film that comprises a silicon nitride film formed over the first film and serves as the charge storage part; and a third film that is formed over the second film and comprises a silicon oxide film, wherein the third film comprises the silicon oxide film and one of a metal and a metal oxide added in atomic or molecular state onto the silicon oxide film, wherein oxide of the metal has a dielectric constant higher than a dielectric constant of silicon oxide, and wherein the metal oxide has a dielectric constant higher than the dielectric constant of silicon oxide.

2 . The semiconductor device according to claim 1 , wherein one of the metal and the metal oxide is added at a surface density of 1×10 13 atoms/cm 2 to 5×10 14 atoms/cm 2 on the silicon oxide film.

3 . The semiconductor device according to claim 1 , wherein the metal comprises one of Hf and Al, and the metal oxide comprises one of HfO 2 and Al 2 O 3 .

4 . The semiconductor device according to claim 1 , wherein the third film is a layer to which Hf, Al, HfO 2 and Al 2 O 3 are added.

5 . The semiconductor device according to claim 4 , wherein the second film comprises a silicon oxynitride film in the silicon nitride film.

6 . The semiconductor device according to claim 5 , further comprising a selection transistor formed in the first region,
wherein the selection transistor comprises: a selection gate electrode disposed alongside the first gate electrode over the semiconductor substrate; and a selection gate insulating film formed between the selection gate electrode and the semiconductor substrate, and wherein the selection gate insulating film is a layer to which one of the metal and the metal oxide is added.

7 . The semiconductor device according to claim 5 , further comprising a first transistor disposed in the second region of the semiconductor substrate,
wherein the first transistor comprises: a second gate electrode disposed over the semiconductor substrate; and a second gate insulating film formed between the second gate electrode and the semiconductor substrate, wherein the second gate insulating film is a layer to which one of the metal and the metal oxide is added.

8 . The semiconductor device according to claim 7 , further comprising:
a second transistor disposed in the third region of the semiconductor substrate, wherein the second transistor comprises: a third gate electrode disposed over the semiconductor substrate; and a third gate insulating film formed between the third gate electrode and the semiconductor substrate, wherein the third gate insulating film is thicker than the second gate insulating film, and is a layer to which one of the metal and the metal oxide is added.

9 . The semiconductor device according to claim 8 ,
wherein the semiconductor substrate comprises a support substrate, an insulating layer disposed over the support substrate, and a semiconductor layer disposed over the insulating layer, wherein the nonvolatile memory cell disposed in the first region is formed in the semiconductor layer, wherein the first transistor disposed in the second region is formed in the support substrate in the second region from which the semiconductor layer and the insulating layer are removed, and wherein the second transistor disposed in the third region is formed in the support substrate in the third region from which the semiconductor layer and the insulating layer are removed.

10 . The semiconductor device according to claim 9 , further comprising a selection transistor formed in the first region,
wherein the selection transistor is formed in the support substrate, and comprises: a selection gate electrode disposed alongside the first gate electrode over the support substrate; and a selection gate insulating film formed between the selection gate electrode and the support substrate, and wherein the selection gate insulating film is a layer to which one of the metal and the metal oxide is added.

11 . A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) providing a semiconductor substrate comprising a first region to form a nonvolatile memory cell; (b) forming a first insulating film for a gate insulating film of the memory cell over the semiconductor substrate; and (c) forming a conductive film over the first insulating film, and patterning the conductive film to form a first gate electrode for the memory cell, wherein the step (b) comprises the steps of: (b1) forming a first film comprising a first silicon oxide film over the semiconductor substrate; (b2) forming a second film over the first film, the second film comprising a silicon nitride film and serving as a charge storage part; and (b3) forming a third film over the second film, the third film comprising a second silicon oxide film and being a layer to which one of a metal and a metal oxide is added, wherein the step (b3) comprises the steps of: (b3-1) forming the second silicon oxide film over the second film; and (b3-2) adding one of the metal and the metal oxide onto the second silicon oxide film in an atomic or molecular state by a sputtering process, wherein oxide of the metal has a dielectric constant higher than a dielectric constant of silicon oxide, and wherein the metal oxide has a dielectric constant higher than the dielectric constant of silicon oxide.

12 . The method according to claim 11 , wherein the metal is one of Hf and Al, and the metal oxide is one of HfO 2 and Al 2 O 3 .

13 . The method according to claim 11 , wherein the third film is a layer to which Hf, Al, HfO 2 and Al 2 O 3 are added, and
wherein the step (b3-2) comprises the steps of: adding Hf onto the second silicon oxide film by a sputtering process using a Hf target, and adding Al onto the second silicon oxide film by a sputtering process using an Al target.

14 . The method according to claim 13 , wherein the step (b2) comprises the steps of:
(b2-1) forming a first silicon nitride film over the first film; (b2-2) oxidizing an upper part of the first silicon nitride film to form a silicon oxynitride film; and (b2-3) forming a second silicon nitride film over the silicon oxynitride film.

15 . A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) providing a semiconductor substrate comprising a first region to forma nonvolatile memory cell, a second region to form a first transistor, and a third region to form a second transistor; (b) forming a first insulating film for a gate insulating film of the first transistor over the semiconductor substrate in each of the first, second, and third regions; (c) after the step (b), removing the first insulating film in the first region to leave the first insulating film in each of the second and third regions; (d) after the step (c), forming a second insulating film for a gate insulating film of the memory cell over the semiconductor substrate in the first region; (e) after the step (d), removing the firs

Assignees

• Renesas Electronics Corp

Inventors

• Abe Shinichiro

Classifications

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• G11C16/0475

  comprising two or more independent storage sites which store independent data · CPC title

• H01L21/28282

  Electricity · mapped topic

• H01L29/792

  Electricity · mapped topic

• H01L29/513

  Electricity · mapped topic