Cache optimization for graphics systems

Patent metadata

Field	Value
Publication number	US-2018307613-A1
Application number	US-201715493757-A
Country	US
Kind code	A1
Filing date	Apr 21, 2017
Priority date	Apr 21, 2017
Publication date	Oct 25, 2018
Grant date	—

Abstract

A mechanism is described for facilitating optimization of cache associated with graphics processors at computing devices. A method of embodiments, as described herein, includes introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

First claim

What is claimed is:

1 . An apparatus comprising:
coloring bit assignment logic, as facilitated by or at least partially incorporated into a processor, to introduce coloring bits to contents of a cache associated with the processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

2 . The apparatus of claim 1 , further comprising detection/observation logic, as facilitated by or at least partially incorporated into the processor, to detect the caches including read-only caches and read/write caches.

3 . The apparatus of claim 1 , further comprising replacement/reallocation logic, as facilitated by or at least partially incorporated into the processor, to regard old coloring bits of the cache as invalid and facilitate replacement or re-allocation of the old coloring bits.

4 . The apparatus of claim 3 , wherein if the cache comprises a read-only cache, the replacement/reallocation logic is further to track the old coloring bits to ensure related entries are reallocated before the color bits are regarded as reusable.

5 . The apparatus of claim 4 , wherein if the cache comprises a read/write cache, the replacement/reallocation logic is further to track old color locations and regard them as a miss.

6 . The apparatus of claim 1 , wherein the coloring bit assignment logic to define the coloring bits and associated with the cache as part of a tag.

7 . The apparatus of claim 1 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

8 . A method comprising:
introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

9 . The method of claim 8 , further comprising detecting the caches including read-only caches and read/write caches.

10 . The method of claim 8 , further comprising regarding old coloring bits of the cache as invalid and facilitating replacement or re-allocation of the old coloring bits.

11 . The method of claim 10 , wherein if the cache comprises a read-only cache, tracking the old coloring bits to ensure related entries are reallocated before the color bits are regarded as reusable.

12 . The method of claim 11 , wherein if the cache comprises a read/write cache, tracking old color locations and regard them as a miss.

13 . The method of claim 8 , further comprising defining the coloring bits and associating the defined color bits with the cache as part of a tag.

14 . The method of claim 8 , wherein the graphics processor is co-located with an application processor on a common semiconductor package.

15 . At least one machine-readable medium comprising instructions that when executed by a computing device, cause the computing device to perform operations comprising:
introducing coloring bits to contents of a cache associated with a processor including a graphics processor, wherein the coloring bits to represent a signal identifying one or more caches available for use, while avoiding explicit invalidations and flushes.

16 . The machine-readable medium of claim 15 , wherein the operations further comprise detecting the caches including read-only caches and read/write caches.

17 . The machine-readable medium of claim 15 , wherein the operations further comprise regarding old coloring bits of the cache as invalid and facilitating replacement or re-allocation of the old coloring bits.

18 . The machine-readable medium of claim 17 , wherein if the cache comprises a read-only cache, tracking the old coloring bits to ensure related entries are reallocated before the color bits are regarded as reusable.

19 . The machine-readable medium of claim 17 , wherein if the cache comprises a read/write cache, tracking old color locations and regard them as a miss.

20 . The machine-readable medium of claim 15 , wherein the operations further comprise defining the coloring bits and associating the defined color bits with the cache as part of a tag, wherein the graphics processor is co-located with an application processor on a common semiconductor package.

Assignees

• Intel Corp

Inventors

• Koker Altug
• Vembu Balaji
• Ray Joydeep
• Appu Abhishek R

Classifications

• G06F12/023

  Free address space management · CPC title

• G06F2212/604

  Details relating to cache allocation · CPC title

• G06F2212/455

  Image or video data · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/1048

  Scalability · CPC title