Multilayer ceramic capacitor and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2018301282-A1
Application number	US-201815908549-A
Country	US
Kind code	A1
Filing date	Feb 28, 2018
Priority date	Apr 17, 2017
Publication date	Oct 18, 2018
Grant date	—

Abstract

A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked wherein: a concentration of a rare earth element of at least one of an end margin region and a side margin region is lower than that of a capacity region; a total concentration of Si and B of the at least one of the end margin region and the side margin region is higher than that of the capacity region.

First claim

What is claimed is:

1 . A multilayer ceramic capacitor comprising:
a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers are alternately stacked, a main component of the plurality of dielectric layers being ceramic, the multilayer structure having a rectangular parallelepiped shape, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, the first edge face facing with the second edge face, wherein: a concentration of a rare earth element of at least one of an end margin region and a side margin region with respect to a main component ceramic is lower than a concentration of the rare earth element of a capacity region with respect to a main component ceramic; a total concentration of Si and B of the at least one of the end margin region and the side margin region with respect to the main component ceramic is higher than a total concentration of Si and B of the capacity region with respect to the main component ceramic; the capacity region is a region in which a set of internal electrode layers exposed to the first edge face of the multilayer structure face with another set of internal electrode layers exposed to the second edge face of the multilayer structure is a capacity region; the end margin region is a region in which internal electrode layers coupled to the first edge face of the multilayer structure face with each other without sandwiching internal electrode layers coupled to the second edge face of the multilayer structure and a region in which internal electrode layers coupled to the second edge face of the multilayer structure face with each other without sandwiching internal electrode layers coupled to the first edge face of the multilayer structure; and the side margin region is a region that covers edge portions to which the plurality of internal electrode layers extend toward two side faces other than the first edge face and the second edge face.

2 . The multilayer ceramic capacitor as claimed in claim 1 , wherein each of concentrations of Mn and Al of the at least one of the end margin region and the side margin region is higher than each of concentrations of Mn and Al of the capacity region.

3 . The multilayer ceramic capacitor as claimed in claim 1 , wherein:
a concentration of V of the capacity region is higher than a concentration of V of the margin region; and a concentration of Mg of the margin region is higher than a concentration of Mg of the capacity region.

4 . The multilayer ceramic capacitor as claimed in claim 1 , further comprising a cover layer on at least one of an upper face and a lower face of the multilayer structure, a main component of the cover layer being the same as a main component of the plurality of dielectric layers.

5 . The multilayer ceramic capacitor as claimed in claim 1 , wherein a main component ceramic of the capacity region, the end margin region and the side margin region is barium titanate.

6 . The multilayer ceramic capacitor as claimed in claim 1 , wherein the total concentration of Si and B of both of the end margin region and the side margin region with respect to the main component ceramic is higher than the total concentration of Si and B of the capacity region with respect to the main component ceramic.

7 . A manufacturing method of a multilayer ceramic capacitor comprising:
a first step of providing a first pattern of a metal conductive paste on a green sheet including main component ceramic grains; a second step of providing a second pattern including main component ceramic grains, on a part of the green sheet around the metal conductive paste; and a third step of baking a ceramic multilayer structure that is obtained by stacking a plurality of layer units obtained in the second step, wherein: a total concentration of Si and B of the second pattern with respect to the main component ceramic of the second pattern is higher than a total concentration of Si and B of the green sheet with respect to the main component ceramic of the green sheet; and a concentration of a rare earth element of the second pattern with respect to the main component ceramic of the second pattern is lower than a concentration of the rare earth element of the green sheet with respect to the main component ceramic of the green sheet.

8 . The manufacturing method of a multilayer ceramic capacitor as claimed in claim 7 , wherein:
the green sheet includes V and does not include Mg; and the second pattern includes Mg and does not include V.

Assignees

• Taiyo Yuden Kk

Inventors

• Nishikawa Jun
• Ueda Shusaku

Classifications

• H01G4/005

  Electrodes · CPC title

• H01G4/1218 Primary

  based on titanium oxides or titanates (H01G4/1245 takes precedence) · CPC title

• H01G4/1236

  based on zirconium oxides or zirconates (H01G4/1263 takes precedence) · CPC title

• C04B35/4682

  based on BaTiO3 perovskite phase · CPC title

• H01G4/30 Primary

  Stacked capacitors (H01G4/33 takes precedence) · CPC title