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High isolation integrated inductor and method thereof
US2018294089A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2018294089-A1 |
| Application number | US-201715481691-A |
| Country | US |
| Kind code | A1 |
| Filing date | Apr 7, 2017 |
| Priority date | Apr 7, 2017 |
| Publication date | Oct 11, 2018 |
| Grant date | — |
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- Title
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Abstract
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An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective.
First claim
Opening claim text (preview).
What is claimed is: 1 . An inductor comprising: a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially symmetrical with respect to a first axis, the second coil of metal trace is laid out to be approximately a mirror image of the first coil of metal trace with respect to a second axis, and the third coil of metal trace is laid out to approximately enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective. 2 . The inductor of claim 1 , wherein the first coil of metal trace includes an opening located on a side farthest away from the second axis. 3 . The inductor of claim 1 , wherein the inductor is housed by a dielectric slab. 4 . The inductor of claim 3 , wherein the dielectric slab is placed on a silicon substrate. 5 . The inductor of claim 4 , wherein another inductor is also fabricated upon the same silicon substrate. 6 . A method comprising: incorporating a first coil of metal trace, configured in an open loop topology, constructed in a first metal layer, and laid out to be substantially symmetrical with respect to a first axis; incorporating a second coil of metal trace, configured in an open loop topology, constructed in the first metal layer, and laid out to be approximately a mirror image of the first coil of metal trace with respect with a second axis; and incorporating a third coil of metal trace, configured in a closed loop topology, constructed in a second metal layer, and laid out to enclose a majority portion of both the first coil of metal trace and the second coil of metal trace from a top view perspective. 7 . The method of claim 6 , wherein the first coil of metal trace includes an opening located on a side farthest away from the second axis. 8 . The method of claim 6 , wherein the inductor is housed by a dielectric slab. 9 . The method of claim 8 , wherein the dielectric slab is placed on a silicon substrate. 10 . The method of claim 9 , wherein another inductor is also fabricated upon the same silicon substrate.
Assignees
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Classifications
Fixed transformers or mutual inductances of the signal type (H01F36/00 takes precedence) · CPC title
Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields · CPC title
- H01F27/2804Primary
Printed windings · CPC title
Manufacture or treatment · CPC title
Printed circuit coils (apparatus or processes for manufacturing printed circuits in general H05K3/00) · CPC title
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- What does patent US2018294089A1 cover?
- An inductor having a first coil of metal trace configured in an open loop topology and placed in a first metal layer; a second coil of metal trace configured in an open loop topology and placed in the first metal layer; and a third coil of metal trace configured in a closed loop topology and placed in a second metal layer, wherein: the first coil of metal trace is laid out to be substantially s…
- Who is the assignee on this patent?
- Realtek Semiconductor Corp
- What technology area does this patent fall under?
- Primary CPC classification H01F27/2804. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Thu Oct 11 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).