Storage device and method of operating the same

Patent metadata

Field	Value
Publication number	US-2018294031-A1
Application number	US-201715818870-A
Country	US
Kind code	A1
Filing date	Nov 21, 2017
Priority date	Apr 11, 2017
Publication date	Oct 11, 2018
Grant date	—

Abstract

Provided herein may be a storage device having disturb characteristics and a method of operating the storage device. The storage device may include one or more semiconductor memory devices, each including a plurality of memory cells, and a memory controller configured to set levels of pass voltages of the one or more semiconductor memory devices depending on program speeds of the plurality of memory cells.

First claim

What is claimed is:

1 . A semiconductor memory device comprising:
a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform operations on the memory cell array; and a control logic configured to control the peripheral circuit based on setting information stored in a contents addressable memory (CAM) block, among the plurality of memory blocks, when the operations are performed, wherein the setting information comprises a level of a pass voltage applied to a plurality of memory cells included in the memory cell array, and wherein the level of the pass voltage is determined depending on program speeds of the plurality of memory cells.

2 . The semiconductor memory device according to claim 1 , wherein the pass voltage comprises a program pass voltage or a read pass voltage that is applied to unselected memory cells during a program operation or a read operation performed on the plurality of memory cells.

3 . The semiconductor memory device according to claim 1 , wherein the pass voltage has a higher level as the program speeds of the plurality of memory cells are higher.

4 . The semiconductor memory device according to claim 1 , wherein the pass voltage is determined depending on program speeds of memory cells at a specific location, among the plurality of memory cells.

5 . The semiconductor memory device according to claim 1 , wherein the pass voltage is determined depending on an average of program speeds of all of the plurality of memory cells.

6 . A storage device, comprising:
one or more semiconductor memory devices, each including a plurality of memory cells; and a memory controller configured to set levels of pass voltages of the one or more semiconductor memory devices depending on program speeds of the plurality of memory cells.

7 . The storage device according to claim 6 , wherein the memory controller comprises:
a voltage setting unit configured to measure the program speeds of the one or more semiconductor memory devices, set the pass voltages depending on the measured program speeds, and provide the pass voltages to the semiconductor memory devices.

8 . The storage device according to claim 7 , wherein the memory controller is configured to transmit a program command for a part or all of the plurality of memory cells, and transmit a read command for acquiring results of execution of the program command.

9 . The storage device according to claim 8 , wherein the memory controller is configured to count a number of off-cells from read data provided by each of the one or more semiconductor memory devices in response to the read command.

10 . The storage device according to claim 9 , wherein the voltage setting unit is configured to compare the number of off-cells with one or more reference values, and determine the pass voltages of the one or more semiconductor memory devices.

11 . The storage device according to claim 6 , wherein the memory controller is configured to provide the pass voltages to the one or more semiconductor memory devices using a parameter set command or a feature set command.

12 . The storage device according to claim 11 , wherein each of the one or more semiconductor memory devices comprises:
a memory cell array including a plurality of memory blocks; a peripheral circuit configured to perform operations on the memory cell array; and a voltage control unit configured to store setting information stored in a contents addressable memory (CAM) block, among the plurality of memory blocks.

13 . The storage device according to claim 12 , wherein each of the one or more semiconductor memory devices further comprises:
a control logic configured to control the peripheral circuit based on the setting information stored in the voltage control unit when the operations are performed.

14 . The storage device according to claim 13 , wherein the control logic is configured to change or update the setting information stored in the voltage control unit in response to the parameter set command or the feature set command provided from the memory controller.

15 . The storage device according to claim 6 , wherein each of the pass voltages has a higher level as program speeds of the plurality of memory cells are higher.

16 . A method of operating a storage device, the storage device including a semiconductor memory device having a plurality of memory cells and a memory controller configured to control the semiconductor memory device, the method comprising:
measuring program speeds of a part or all of the plurality of memory cells; and setting a level of a pass voltage of the semiconductor memory device depending on the measured program speeds.

17 . The method according to claim 16 , wherein the pass voltage comprises a program pass voltage or a read pass voltage that is applied to unselected memory cells during a program operation or a read operation performed on the plurality of memory cells.

18 . The method according to claim 16 , wherein the pass voltage has a higher level as the program speeds of the plurality of memory cells are higher.

19 . The method according to claim 16 , wherein the measuring comprises:
performing a program operation on a part or all of the plurality of memory cells; and performing a read operation on memory cells on which the program operation has been performed.

20 . The method according to claim 19 , wherein the setting is configured to set the pass voltage based on a number of off-cells in read data acquired during the read operation.

Assignees

• Sk Hynix Inc

Inventors

• Seo Ji Hyun

Classifications

• G11C15/046 Primary

  using non-volatile storage elements · CPC title

• G11C16/3418 Primary

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title