Semiconductor packages and methods for fabricating semiconductor packages

Patent metadata

Field	Value
Publication number	US-2018290882-A1
Application number	US-201615574349-A
Country	US
Kind code	A1
Filing date	Jun 10, 2016
Priority date	Jun 17, 2015
Publication date	Oct 11, 2018
Grant date	—

Abstract

According to various embodiments, there is provided a method for fabricating a semiconductor package, the method including forming a cap structure and a pillar from a first wafer; bonding the first wafer to a second wafer; and filling a gap between the pillar and the cap structure with a mold compound.

First claim

1 . A method for fabricating a semiconductor package, the method comprising:
forming a cap structure and a pillar from a first wafer; bonding the first wafer to a second wafer; and filling a gap between the pillar and the cap structure with a mold compound.

2 . The method of claim 1 , wherein the gap between the pillar and the cap structure is filled with the mold compound after the first wafer is bonded to the second wafer.

3 . The method of claim 1 , further comprising:
forming at least one of a bonding pad or a sealing ring on the first wafer.

4 . The method of claim 1 , wherein forming the cap structure and the pillar from the first wafer comprises forming a cavity and a groove in the first wafer.

5 . The method of claim 4 , wherein forming the cavity and the groove in the first wafer comprises a first etching step and a second etching step.

6 . The method of claim 5 , wherein the first etching step comprises forming the groove and wherein the second etching step comprises forming the cavity, wherein the cavity has a different depth from the groove.

7 . The method of claim 4 , further comprising:
depositing a metal layer on the first wafer after forming the cavity and the groove in the first wafer.

8 . The method of claim 4 , wherein an inner surface of the first wafer is bonded to the second wafer after the cavity and the groove are formed, wherein the inner surface is a surface of the first wafer whereat the groove and the cavity are formed.

9 . The method of claim 4 , wherein forming the cap structure and the pillar from the first wafer further comprises removing part of the first wafer at an end of the groove to form the gap.

10 . The method of claim 4 , further comprising:
forming a further groove in the first wafer, wherein part of the first wafer at an end of the further groove is removed to form a further gap, wherein the further gap separates a further pillar from the pillar.

11 . The method of claim 1 , further comprising:
grounding away part of the mold compound to expose the cap structure and the pillar.

12 . The method of claim 1 , further comprising:
providing a redistribution layer over a top surface of the mold compound, a top end of the pillar and a top surface of the cap structure, wherein each of the top surface of the mold compound, the top end of the pillar and the top surface of the cap structure face away from the second wafer.

13 . The method of claim 12 , wherein the top surface of the mold compound, the top end of the pillar and the top surface of the cap structure form a flat surface.

14 . A semiconductor package comprising:
a cap structure and a pillar formed from a first wafer; a second wafer bonded to the cap structure and the pillar; and a mold compound between the pillar and the cap structure.

15 . The semiconductor package of claim 14 , wherein the second wafer comprises a MEMS device.

16 . The semiconductor package of claim 14 , wherein the first wafer comprises conductive silicon.

17 . The semiconductor package of claim 14 , further comprising:
at least one of a sealing ring on the cap structure or a bonding pad on the pillar.

18 . The semiconductor package of claim 14 , wherein each of the pillar and the cap structure comprises a metal layer.

19 . The semiconductor package of claim 14 , further comprising:
a further pillar, wherein the further pillar is separated from the pillar by a further gap.

20 . The semiconductor package of claim 14 , further comprising:
a redistribution layer over a top surface of the mold compound, a top end of the pillar and a top surface of the cap structure, wherein each of the top surface of the mold compound, the top end of the pillar and the top surface of the cap structure face away from the second wafer.

Assignees

• Agency Science Tech & Res

Inventors

• Rhee Daniel Minwoo
• Chang Peter Hyun Kee

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title