Shift register and driving method thereof, gate driving circuit and display apparatus

Patent metadata

Field	Value
Publication number	US-2018286342-A1
Application number	US-201715792603-A
Country	US
Kind code	A1
Filing date	Oct 24, 2017
Priority date	Mar 29, 2017
Publication date	Oct 4, 2018
Grant date	—

Abstract

The present disclosure provides a shift register and a driving method thereof, a gate driving circuit, and a display apparatus. The shift register comprises an input circuit, a first output circuit, a second output circuit, and a negative voltage switching circuit. The input circuit has an input terminal configured to receive an input signal, an output terminal coupled to a first node, and a control terminal configured to receive a first clock signal. The first output circuit has an input terminal configured to receive a second clock signal, an output terminal coupled to an output signal terminal, and a control terminal coupled to the first node. The second output circuit has an input terminal configured to receive a first low level signal, an output terminal coupled to the output signal terminal, and a control terminal configured to receive a third clock signal. The negative voltage switching circuit has an input terminal configured to receive a second low level signal, an output terminal coupled to the first node, and a control terminal configured to receive a fourth clock signal.

First claim

I/We claim:

1 . A shift register, comprising:
an input circuit having an input terminal configured to receive an input signal, an output terminal coupled to a first node, and a control terminal configured to receive a first clock signal, and configured to transfer the input signal to the first node under control of the first clock signal; a first output circuit having an input terminal configured to receive a second clock signal, an output terminal coupled to an output signal terminal, and a control terminal coupled to the first node, and configured to transfer the second clock signal to the output signal terminal under control of the first node; a second output circuit having an input terminal configured to receive a first low level signal, an output terminal coupled to the output signal terminal, and a control terminal configured to receive a third clock signal, and configured to transfer the first low level signal to the output signal terminal under control of the third clock signal; and a negative voltage switching circuit having an input terminal configured to receive a second low level signal, an output terminal coupled to the first node, and a control terminal configured to receive a fourth clock signal, and configured to transfer the second low level signal to the first node under control of the fourth clock signal, wherein the input signal has a different level from that of the second low level signal.

2 . The shift register according to claim 1 , wherein the third clock signal and the first clock signal are the same.

3 . The shift register according to claim 1 , wherein the input circuit comprises a first transistor, and wherein the input terminal of the input circuit is one of a source and a drain of the first transistor, the output terminal of the input circuit is the other of the source and the drain of the first transistor, and the control terminal of the input circuit is a gate of the first transistor.

4 . The shift register according to claim 1 , wherein the first output circuit comprises a second transistor and a capacitor, and wherein the input terminal of the first output circuit is one of a source and a drain of the second transistor, the output terminal of the first output circuit is the other of the source and the drain of the second transistor, and the control terminal of the first output circuit is a gate of the second transistor, and wherein the capacitor has a first terminal coupled to the first node and a second terminal coupled to the output signal terminal.

5 . The shift register according to claim 1 , wherein the second output circuit comprises a third transistor, and wherein the input terminal of the second output circuit is one of a source and a drain of the third transistor, the output terminal of the second output circuit is the other of the source and the drain of the third transistor, and the control terminal of the second output circuit is a gate of the third transistor.

6 . The shift register according to claim 1 , wherein the negative voltage switching circuit comprises a fourth transistor, and wherein the input terminal of the negative voltage switching circuit is one of a source and a drain of the fourth transistor, the output terminal of the negative voltage switching circuit is the other of the source and the drain of the fourth transistor, and the control terminal of the negative voltage switching circuit is a gate of the fourth transistor.

7 . A gate driving circuit comprising a plurality of cascaded shift registers according to claim 1 .

8 . A display apparatus comprising the gate driving circuit according to claim 7 .

9 . A driving method for driving the shift register according to claim 1 , comprising:
a first pull-down stage in which the input circuit is controlled to be switched off by the first clock signal, and the negative voltage switching circuit is controlled to be switched on by the fourth clock signal, so that a voltage at the first node is reduced to a third level, and the output signal terminal outputs a low level; a second pull-down stage including a first period and a second period,
wherein in the first period, the input circuit is controlled to be switched on by the first clock signal, and the negative voltage switching circuit is controlled to be switched off by the fourth clock signal, so that the voltage at the first node is reduced to a fourth level, and the output signal terminal outputs the low level; and
wherein in the second period, the input circuit and the negative voltage switching circuit are controlled to be switched off by the first clock signal and the fourth clock signal, so that the voltage at the first node is maintained at the fourth level, and the output signal terminal outputs the low level,
wherein the third level is different from the fourth level.

10 . The method according to claim 9 , wherein before the first pull-down stage, the method further comprises:
a first pull-up stage in which the input circuit and the second output circuit are controlled to be switched on by the first clock signal and the third clock signal, the negative voltage switching circuit is controlled to be switched off by the fourth clock signal, and the second clock signal having the low level is inputted, so that the voltage at the first node is raised to a first level, and the output signal terminal outputs the low level; and a second pull-up stage in which the input circuit and the negative voltage switching circuit are controlled to be switched off by the first clock signal and the fourth clock signal, and the second clock signal having a high level is inputted, so that the voltage at the first node is further raised to a second level, and the output signal terminal outputs the high level.

11 . The method according to claim 9 , wherein the first pull-down stage and the second pull-down stage are alternated, so that the voltage at the first node is periodically changed between the third level and the fourth level.

12 . The method according to claim 9 , wherein the third level is a different negative level from the fourth level.

13 . The method according to claim 9 , wherein the third level is higher than the fourth level.

Assignees

• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoelectronics Technology Co Ltd

Inventors

• Li Meng
• Wang Ying

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0264

  Details of driving circuits · CPC title

• G09G2320/045

  Compensation of drifts in the characteristics of light emitting or modulating elements · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title