Method to synthesize a cross bar switch in a highly congested environment

Patent metadata

Field	Value
Publication number	US-2018285486-A1
Application number	US-201715472441-A
Country	US
Kind code	A1
Filing date	Mar 29, 2017
Priority date	Mar 29, 2017
Publication date	Oct 4, 2018
Grant date	—

Abstract

A facility is provided for automatically generating design data for a semiconductor circuit including a crossbar switch. The method includes synthesizing the crossbar switch using predefined multiplexer building blocks, where the predefined multiplexer building blocks include at least a multiplexer, an input driver and a select driver. In addition, the method includes regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement, testing the crossbar switch arrangement for timing constraints and re-synthesizing the crossbar switch and/or replacing the predefined multiplexer building blocks based on the testing.

First claim

What is claimed is:

1 . A method for automatically generating design data for a semiconductor circuit comprising a crossbar switch, wherein the method comprises:
synthesizing the crossbar switch using predefined multiplexer building blocks, wherein the predefined multiplexer building blocks comprise at least a multiplexer, an input driver and a select driver; regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement; testing the crossbar switch arrangement for timing constraints; and re-synthesizing the crossbar switch or replacing of the predefined multiplexer building blocks based on the testing.

2 . The method according to claim 1 , wherein the method comprises repeating the testing and the re-synthesizing or replacing with amended synthesizing or placing parameters.

3 . The method according to claim 1 , wherein re-synthesizing of the crossbar switch comprises splitting the depth of the multiplexers.

4 . The method according to claim 3 , wherein splitting the multiplexer depth comprises dividing the multiplexer depth by three.

5 . The method according to claim 3 , wherein splitting the multiplexer depth comprises dividing the multiplexer depth by two.

6 . The method according to claim 1 , wherein replacing comprises placing an input driver in the center of two multiplexers.

7 . The method according to claim 1 , wherein:
the re-synthesizing comprises using multiplexers comprising multiple multiplexer areas; one of said multiplexer areas comprise a primary output driver and the remaining multiplexer areas include the multiplexing circuits; and the replacing comprises placing the multiplexer such that the multiplexer area are located in adjacent bit bay areas, wherein a single bit bay area includes two power supply rails.

8 . The method of claim 7 , wherein the replacing comprises placing the multiplexers such that the multiplexer areas including the multiplexing circuit of neighboring multiplexers are located spaced apart from each other.

9 . The method of claim 1 , wherein re-synthesizing comprises using additional select drivers and replacing comprises connecting fewer multiplexers to each select driver.

10 . A computer program product for generating design data for a semiconductor circuit comprising a crossbar switch, the computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code being executable by a processor to perform a method comprising:
synthesizing the crossbar switch using predefined multiplexer building blocks, wherein the predefined multiplexer building blocks comprise at least a multiplexer, an input driver and a select driver;
regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement;
testing the crossbar switch arrangement for timing constraints; and
re-synthesizing the crossbar switch or replacing of the predefined multiplexer building blocks based on the testing.

11 . The computer program product of claim 10 , wherein the method comprises repeating the testing and the re-synthesizing or replacing with amended synthesizing or placing parameters.

12 . The computer program product of claim 10 , wherein re-synthesizing of the crossbar switch comprises splitting the depth of the multiplexers.

13 . The computer program product of claim 12 , wherein splitting the multiplexer depth comprises dividing the multiplexer depth by three.

14 . The computer program product of claim 12 , wherein splitting the multiplexer depth comprises dividing the multiplexer depth by two.

15 . The computer program product of claim 10 , wherein replacing comprises placing an input driver in the center of two multiplexers.

16 . The computer program product of claim 10 , wherein:
the re-synthesizing comprises using multiplexers comprising multiple multiplexer areas; one of said multiplexer areas comprise a primary output driver and the remaining multiplexer areas include the multiplexing circuits; and the replacing comprises placing the multiplexer such that the multiplexer area are located in adjacent bit bay areas, wherein a single bit bay area includes two power supply rails.

17 . The computer program product of claim 16 , wherein the replacing comprises placing the multiplexers such that the multiplexer areas including the multiplexing circuit of neighboring multiplexers are located spaced apart from each other.

18 . The computer program product of claim 10 , wherein re-synthesizing comprises using additional select drivers and replacing comprises connecting fewer multiplexers to each select driver.

19 . A system for automatically generating design data for a semiconductor circuit comprising a crossbar switch, the system comprising:
a memory; and a processor communicatively coupled to the memory, wherein the system performs a method comprising:
synthesizing the crossbar switch using predefined multiplexer building blocks, wherein the predefined multiplexer building blocks comprise at least a multiplexer, an input driver and a select driver;
regularly placing the predefined multiplexer building blocks to define a crossbar switch arrangement;
testing the crossbar switch arrangement for timing constraints; and
re-synthesizing the crossbar switch or replacing of the predefined multiplexer building blocks based on the testing.

20 . The system of claim 19 , wherein re-synthesizing of the crossbar switch comprises splitting the depth of the multiplexers.

Assignees

• IBM

Inventors

• Lind Kurt
• Schroeder Friedrich

Classifications

• G06F30/392 Primary

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/327 Primary

  Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist · CPC title

• G06F17/505 Primary

  Physics · mapped topic

• G06F17/5072

  Physics · mapped topic

• G06F17/5081

  Physics · mapped topic