Comparator and successive approximation analog-to-digital converter thereof

Patent metadata

Field	Value
Publication number	US-2018262203-A1
Application number	US-201815916517-A
Country	US
Kind code	A1
Filing date	Mar 9, 2018
Priority date	Mar 9, 2017
Publication date	Sep 13, 2018
Grant date	—

Abstract

A comparator and a successive approximation analog-to-digital converter are provided. The comparator includes a pre-operational amplifier, a latch, a level shift unit, and a reset unit. The pre-operational amplifier receives a to-be-compared signal, and outputs a first-stage amplification signal and a latch clock signal. The latch includes a first inverter circuit and a second inverter circuit, receives and compares the first-stage amplification signal, and outputs a comparison result signal. The level shift unit includes a first level shift circuit and a second level shift circuit, and generates a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively. The reset unit includes a first reset circuit and a second reset circuit, and resets a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.

First claim

What is claimed is:

1 . A comparator, comprising:
a pre-operational amplifier, for receiving a to-be-compared signal inputted to the comparator, and outputting a first-stage amplification signal according to the to-be-compared signal and a latch clock signal; a latch, including a first inverter circuit and a second inverter circuit that have a same structure and are symmetrically configured, and for receiving and comparing the first-stage amplification signal, and outputting a corresponding comparison result signal according to a comparison result; a level shift unit, including a first level shift circuit and a second level shift circuit that are symmetrically configured, and for generating a potential difference between working transistors in the first inverter circuit and the second inverter circuit, respectively; and a reset unit, including a first reset circuit and a second reset circuit that are symmetrically configured, and for resetting a voltage of a node where the level shift unit, the first inverter circuit and the second inverter circuit are coupled when the latch clock signal is at a low level.

2 . The comparator according to claim 1 , wherein:
the first inverter circuit and the second inverter circuit are connected in parallel between a reference power supply and a reference ground; a signal input terminal of the first inverter circuit is connected to a signal output terminal of the second inverter circuit, and a signal output terminal of the first inverter circuit is connected to a signal input terminal of the second inverter circuit; the first level shift circuit is coupled to the reset unit and the first inverter circuit, and is adapted to turn on the first inverter circuit when the comparator jumps from a reset state to a comparison state; the second level shift circuit is coupled to the reset unit and the second inverter circuit, and is adapted to turn on the second inverter circuit when the comparator jumps from the reset state to the comparison state; the first reset circuit is coupled to the first level shift circuit and the first inverter circuit; and the second reset circuit is coupled to the second level shift circuit and the second inverter circuit.

3 . The comparator according to claim 2 , wherein:
the first level shift circuit includes a third PMOS transistor coupled to the first inverter circuit; and the second level shift circuit includes a fourth PMOS transistor coupled to the second inverter circuit.

4 . The comparator according to claim 2 , wherein:
the first reset circuit includes a fourth NMOS transistor coupled to the first inverter circuit; and the second reset circuit includes a fifth NMOS transistor coupled to the second inverter circuit.

5 . The comparator according to claim 2 , wherein:
the pre-operational amplifier includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, and a second PMOS transistor.

6 . The comparator according to claim 5 , wherein:
a gate of the first NMOS transistor is coupled to the latch clock signal, a source of the first NMOS transistor is coupled to the reference ground, and a drain of the first NMOS transistor is coupled to a source of the second NMOS transistor and a source of the third NMOS transistor; a gate of the second NMOS transistor is coupled to a first to-be-compared signal, the source of the second NMOS transistor is coupled to the drain of the first NMOS transistor and the source of the third NMOS transistor, and a drain of the second NMOS transistor is coupled to a drain of the first PMOS transistor; a gate of the third NMOS transistor is coupled to a second to-be-compared signal, the source of the third NMOS transistor is coupled to the drain of the first NMOS transistor and the source of the second NMOS transistor, and a drain of the third NMOS transistor is coupled to a drain of the second PMOS transistor; a gate of the first PMOS transistor is coupled to the latch clock signal, a source of the first PMOS transistor is coupled to a reference power supply, and the drain of the first PMOS transistor is coupled to the drain of the second NMOS transistor; and a gate of the second PMOS transistor is coupled to the latch clock signal, a source of the second PMOS transistor is coupled to the reference power supply, and the drain of the second PMOS transistor is coupled to the drain of the third NMOS transistor.

7 . The comparator according to claim 6 , wherein:
an intersection where the drain of the second NMOS transistor and the drain of the first PMOS transistor are coupled serves as a node for outputting a first-stage amplification signal; and an intersection where the drain of the third NMOS transistor and the drain of the second PMOS transistor are coupled serves as a node for outputting a second-stage amplification signal.

8 . The comparator according to claim 7 , wherein:
the first inverter circuit includes a sixth NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, a fifth PMOS transistor, and a seventh PMOS transistor.

9 . The comparator according to claim 8 , wherein:
a gate of the sixth NMOS transistor is coupled to the node for outputting the first-stage amplification signal, a source of the sixth NMOS transistor is coupled to the reference ground, and a drain of the sixth NMOS transistor is coupled to a drain of the third PMOS transistor and a drain of the eighth NMOS transistor; a gate of the eighth NMOS transistor is coupled to a drain of the fifth NMOS transistor, a source of the eighth NMOS transistor is coupled to the reference ground, and a drain of the eighth NMOS transistor is coupled to the drain of the sixth NMOS transistor and the drain of the third PMOS transistor; a gate of the third PMOS transistor is coupled to the reference ground, a source of the third PMOS transistor is coupled to a drain of the fourth NMOS transistor and a drain of the fifth PMOS transistor, and the drain of the third PMOS transistor is coupled to the drain of the sixth NMOS transistor and the drain of the eighth NMOS transistor; a gate of the fifth PMOS transistor is coupled to a gate of the fourth NMOS transistor and the gate of the sixth NMOS transistor, a source of the fifth PMOS transistor is coupled to a drain of the seventh PMOS transistor, and the drain of the fifth PMOS transistor is coupled to the drain of the fourth NMOS transistor and the source of the third PMOS transistor; and a gate of the seventh PMOS transistor is coupled to a drain of the fourth PMOS transistor, a source of the seventh PMOS transistor is coupled to the reference power supply, and the drain of the seventh PMOS transistor is coupled to the source of the fifth PMOS transistor.

10 . The comparator according to claim 9 , wherein:
an intersection where the drain of the eighth NMOS transistor, the drain of the sixth NMOS transistor and the drain of the third PMOS transistor are coupled serves as a node for outputting a first comparison result signal.

11 . The comparator according to claim 10 , wherein:
the second inverter circuit includes a seventh NMOS transistor, a ninth NMOS transistor, a fourth PMOS transistor, a sixth PMOS transistor, and an eighth PMOS transistor.

12 . The comparator according to claim 11 , wherein:
a gate of the seventh NMOS transistor is coupled to a gate of the fifth NMOS transistor and a gate of the sixth PMOS transistor, a source of the seventh NMOS transistor is coupled to the reference ground, and a drain of the seventh NMOS transistor is coupled to the drain of the fourth PMOS transistor and a drain of the ninth NMOS transistor; a gate of the ninth NMOS transisto

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Yang hai feng
• Tang Hua
• Liu Fei
• XUN Ben Peng
• Zhu Xiao Ming

Classifications

• H03M1/069

  by range overlap between successive stages or steps · CPC title

• H03M1/466 Primary

  using switched capacitors · CPC title

• H03K5/2481 Primary

  with at least one differential stage · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title