Three dimensional semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-2018261618-A1
Application number	US-201715722485-A
Country	US
Kind code	A1
Filing date	Oct 2, 2017
Priority date	Mar 9, 2017
Publication date	Sep 13, 2018
Grant date	—

Abstract

A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.

First claim

1 . A three-dimensional semiconductor device, comprising:
a substrate including a first area and a second area; a first gate electrode and a second gate electrode, sequentially stacked on the first area of the substrate and extending parallel to a surface of the substrate and in a first direction from the first area to the second area, each of the first gate electrode and the second gate electrode including a first cell gate portion disposed on the first area and a first gate extension portion and a second gate extension portion extended from the first cell gate portion in the first direction, the first gate electrode including a first pad portion, and the second gate electrode including a second pad portion; and channel structures disposed in the first area of the substrate and penetrating through the first gate electrode and the second gate electrode, wherein the second pad portion of the second gate electrode is disposed on an end portion of the second gate extension portion of the second gate electrode, and wherein the second gate electrode includes a protruding portion disposed on an end portion of the first gate extension portion of the second gate electrode.

2 . The three-dimensional semiconductor device of claim 1 , wherein the second pad portion and the protruding portion have the same thickness and different widths.

3 . The three-dimensional semiconductor device of claim 1 , wherein a width of the second pad portion in a second direction, perpendicular to the first direction and parallel to the surface of the substrate is greater than a width of the protruding portion in the second direction.

4 . The three-dimensional semiconductor device of claim 1 , wherein the protruding portion of the second gate electrode overlaps the first gate extension portion of the first gate electrode.

5 . The three-dimensional semiconductor device of claim 1 , wherein the second pad portion does not overlap the first pad portion.

6 . The three-dimensional semiconductor device of claim 1 , wherein each of the first gate electrode and the second gate electrode comprises a second cell gate portion disposed on the first area and disposed to be spaced apart from the first cell gate portion, a third gate extension portion and a fourth gate extension portion, extended from the second cell gate portion in the first direction, and a gate connection portion connecting the first cell gate portion and the second cell gate portion to the first gate extension portion, the second gate extension portion, the third gate extension portion, and the fourth gate extension portion, and
wherein the first gate extension portion, the second gate extension portion, the third gate extension portion, and the fourth gate extension portion are sequentially arranged in a second direction, perpendicular to the first direction and parallel to the surface of the substrate.

7 . The three-dimensional semiconductor device of claim 6 , further comprising:
a third gate electrode on the second gate electrode; and a fourth gate electrode on the third gate electrode, wherein each of the first gate electrode, the second gate electrode, the third gate electrode, and the fourth gate electrode includes the first cell gate portion, the second cell gate portion, the first gate extension portion, the second gate extension portion, the third gate extension portion, the fourth gate extension portion, and the gate connection portion.

8 . The three-dimensional semiconductor device of claim 7 , wherein the third gate electrode comprises a third pad portion disposed on an end portion of the third gate extension portion of the third gate electrode,
wherein the fourth gate electrode comprises a fourth pad portion disposed on an end portion of the fourth gate extension portion of the fourth gate electrode, and wherein the first pad portion, the second pad portion, the third pad portion, and the fourth pad portion do not overlap.

9 . The three-dimensional semiconductor device of claim 8 , wherein the third gate electrode comprises a protruding portion disposed on an end portion of the second gate extension portion of the third gate electrode, and
wherein the fourth gate electrode comprises a protruding portion disposed on an end portion of the third gate extension portion of the fourth gate electrode.

10 . The three-dimensional semiconductor device of claim 1 , wherein the protruding portion comprises a portion, a thickness of which is increased in the first direction, and
wherein each of the first pad portion and the second pad portion comprises a portion, a thickness of which is increased in the first direction and a portion, a thickness of which is increased in a second direction perpendicular to the first direction.

11 . A three-dimensional semiconductor device, comprising:
a substrate including a first area and a second area; a first main separation pattern and a second main separation pattern, disposed on the substrate and intersecting the first area and the second area of the substrate; gate electrodes disposed between the first main separation pattern and the second main separation pattern and forming a stacked gate group, the gate electrodes sequentially stacked on the first area of the substrate and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area of the substrate, disposed between the first main separation pattern and the second main separation pattern, and penetrating through the gate electrodes disposed on the second area of the substrate, wherein each of the gate electrodes includes a pad portion on the second area of the substrate, and wherein the pad portion is thicker than the each of the gate electrodes disposed on the first area and contacts the at least one secondary separation pattern.

12 . The three-dimensional semiconductor device of claim 11 , wherein the pad portions of the gate electrodes are arranged to have a stepped structure formed downwardly by a first height in a direction from the first main separation pattern to the second main separation pattern and arranged to have a stepped structure formed downwardly by a second height greater than the first height in a direction from the first area to the second area.

13 . The three-dimensional semiconductor device of claim 11 , further comprising:
a string select line on the stacked gate group; channel structures extending from a surface of the first area of the substrate in a direction perpendicular to a surface of the substrate and penetrating through the stacked gate group and the string select line; and a cell secondary separation pattern disposed on the first area of the substrate between the first main separation pattern and the second main separation pattern and penetrating through the string select line and the stacked gate group, wherein the gate electrodes forming the stacked gate group include word lines, and wherein the cell secondary separation pattern is spaced apart from the at least one secondary separation pattern.

14 . The three-dimensional semiconductor device of claim 11 , wherein the at least one secondary separation pattern comprises a first secondary separation pattern and a second secondary separation pattern,
wherein the first secondary separation pattern is disposed between the first main separation pattern and the second main separation pattern, and wherein the second secondary separation pattern is disposed between the first secondary separation pattern and the first main separation pattern and between the second secondary separation pattern and the second main separation pattern

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Chang Sup
• Nam Phil Ouk
• Lee Sung Yun
• Kang Chang Seok

Classifications

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic