Semiconductor device contacts with increased contact area

Patent metadata

Field	Value
Publication number	US-2018248011-A1
Application number	US-201515754887-A
Country	US
Kind code	A1
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Aug 30, 2018
Grant date	—

Abstract

Semiconductor contact architectures are provided, wherein contact metal extends into the semiconductor layer to which contact is being made, thereby increasing contact area. An offset spacer allows a relatively deep etch into the semiconductor material to be achieved. Thus, rather than just a flat horizontal surface of the semiconductor being exposed for contact area, relatively long vertical trench sidewalls and a bottom wall are exposed and available for contact area. The trench can then be filled with the desired contact metal. Doping of the semiconductor layer into which the contact is being formed can be carried out in a manner that facilitates an efficient contact trench etch process, such as by, for example, utilization of post trench etch doping or a semiconductor layer having an upper undoped region through which the contact trench etch passes and a lower doped S/D region. The offset spacer may be removed from final structure.

First claim

1 . A semiconductor device, comprising:
a body including semiconductor material; a gate structure at least over the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the gate electrode and the body; a source region and a drain region, the body between the source and drain regions, wherein the source and drain regions include semiconductor material; a first trench extending into the source region and a second trench extending into the drain region; and a first contact structure within the first trench and a second contact structure within the second trench, the first and second contact structures including metal.

2 . The device of claim 1 wherein each of the first and second trenches has a bottom and a top, and the device further comprises a pair of offset spacers at the top of each of the first and second trenches.

3 . The device of claim 2 wherein a portion of the first contact structure is between corresponding offset spacers, and a portion of the second contact structure is between corresponding offset spacers.

4 . The device of claim 2 wherein each of the pairs of offset spacers is on top of the semiconductor material included in the source and drain regions.

5 . The device of claim 2 wherein one of the offset spacers is in contact with a gate spacer, the gate spacer adjacent the gate structure.

6 . The device of claim 5 wherein the one of the offset spacers and the gate spacer comprise the same material.

7 . The device of claim 1 wherein the body comprises compositionally different semiconductor material relative to an underlying substrate.

8 . The device of claim 1 wherein the body is a fin, and the fin is between portions of the gate structure.

9 . The device of claim 1 wherein the body is a nanowire, and the gate structure is around the nanowire.

10 . The device of claim 1 wherein the source and drain regions are raised such that they extend beyond the top of the body.

11 . The device of claim 1 wherein the source and drain regions include a graded doping scheme that includes lower doping in areas through which the corresponding first or second trench passes and higher doping in other areas.

12 . The device of claim 1 wherein the source and drain regions each include a doped portion and an undoped portion.

13 . The device of claim 12 wherein each of the first and second trenches passes through the corresponding undoped portion and ends proximate to or in the doped portion.

14 . The device of claim 1 wherein the first and second trenches have a rectangular or tapered shape.

15 . The device of claim 1 wherein the device is part of a computing device.

16 . The device of claim 15 wherein the computing device is a mobile computing device.

17 . An integrated circuit including at least one transistor, the integrated circuit comprising:
a fin extending vertically from a substrate, the fin including semiconductor material; a gate structure at least over the fin, the gate structure including a gate electrode and a gate dielectric, the gate dielectric between the gate electrode and the fin; a source region and a drain region, the fin between the source and drain regions, wherein the source and drain regions include semiconductor material; a first trench extending into the source region and a second trench extending into the drain region, the first trench having a depth that is at least 25% of the total vertical length of the source region, and the second trench having a depth that is at least 25% of the total vertical length of the drain region; and a first contact structure substantially filling the first trench and a second contact structure substantially filling the second trench, the first and second contact structures including metal.

18 . The integrated circuit of claim 17 , further comprising:
a pair of offset spacers at the top of each of the first and second trenches, wherein each of the first and second trenches continues through the corresponding pair of offset spacers.

19 - 25 . (canceled)

26 . An integrated circuit including at least one transistor, the integrated circuit comprising:
a body including semiconductor material; a gate structure at least over the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the gate electrode and the body; a source region and a drain region, the body between the source and drain regions, wherein the source and drain regions include semiconductor material; a first trench in the source region and a second trench in the drain region, wherein the first trench extends down at least 20 nanometers (nm) from a top surface of the source region, and the second trench extends down at least 20 nm from a top surface of the drain region; and a first contact structure in the first trench and a second contact structure in the second trench, the first and second contact structures including metal.

27 . The integrated circuit of claim 26 further comprising a pair of offset spacers at the top of each of the first and second trenches, wherein each of the first and second trenches continues through the corresponding pair of offset spacers.

Assignees

• Intel Corp

Inventors

• Mehandru Rishabh
• Ghani Tahir
• Liao Szuya S

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/642

  Chemical etching · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10W20/0698

  Local interconnections · CPC title